1*c9017cbcSGovindraj Raja /* 2*c9017cbcSGovindraj Raja * Copyright (c) 2026, Arm Limited. All rights reserved. 3*c9017cbcSGovindraj Raja * 4*c9017cbcSGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*c9017cbcSGovindraj Raja */ 6*c9017cbcSGovindraj Raja 7*c9017cbcSGovindraj Raja #ifndef ROSILLO_H 8*c9017cbcSGovindraj Raja #define ROSILLO_H 9*c9017cbcSGovindraj Raja 10*c9017cbcSGovindraj Raja #define ROSILLO_MIDR U(0x410FDA10) 11*c9017cbcSGovindraj Raja 12*c9017cbcSGovindraj Raja /******************************************************************************* 13*c9017cbcSGovindraj Raja * CPU Extended Control register specific definitions 14*c9017cbcSGovindraj Raja ******************************************************************************/ 15*c9017cbcSGovindraj Raja #define ROSILLO_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16*c9017cbcSGovindraj Raja 17*c9017cbcSGovindraj Raja /******************************************************************************* 18*c9017cbcSGovindraj Raja * CPU Power Control register specific definitions 19*c9017cbcSGovindraj Raja ******************************************************************************/ 20*c9017cbcSGovindraj Raja #define ROSILLO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*c9017cbcSGovindraj Raja #define ROSILLO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22*c9017cbcSGovindraj Raja 23*c9017cbcSGovindraj Raja #endif /* ROSILLO_H */ 24*c9017cbcSGovindraj Raja 25