1328d304dSSona Mathew /* 2037a15f5SArvind Ram Prakash * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3328d304dSSona Mathew * 4328d304dSSona Mathew * SPDX-License-Identifier: BSD-3-Clause 5328d304dSSona Mathew */ 6328d304dSSona Mathew 7328d304dSSona Mathew #ifndef NEOVERSE_V3_H 8328d304dSSona Mathew #define NEOVERSE_V3_H 9328d304dSSona Mathew 10328d304dSSona Mathew 11328d304dSSona Mathew #define NEOVERSE_V3_VNAE_MIDR U(0x410FD830) 12328d304dSSona Mathew #define NEOVERSE_V3_MIDR U(0x410FD840) 13328d304dSSona Mathew 14328d304dSSona Mathew /******************************************************************************* 15328d304dSSona Mathew * CPU Extended Control register specific definitions. 16328d304dSSona Mathew ******************************************************************************/ 17328d304dSSona Mathew #define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4 18328d304dSSona Mathew 19328d304dSSona Mathew /******************************************************************************* 20328d304dSSona Mathew * CPU Power Control register specific definitions 21328d304dSSona Mathew ******************************************************************************/ 22328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 23328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 24328d304dSSona Mathew 25037a15f5SArvind Ram Prakash /******************************************************************************* 26037a15f5SArvind Ram Prakash * CPU Auxiliary control register 6 specific definitions 27037a15f5SArvind Ram Prakash ******************************************************************************/ 28037a15f5SArvind Ram Prakash #define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1 29037a15f5SArvind Ram Prakash 30*e25fc9dfSGovindraj Raja #ifndef __ASSEMBLER__ 31*e25fc9dfSGovindraj Raja long check_erratum_neoverse_v3_3701767(long cpu_rev); 32*e25fc9dfSGovindraj Raja #endif /* __ASSEMBLER__ */ 33*e25fc9dfSGovindraj Raja 34328d304dSSona Mathew #endif /* NEOVERSE_V3_H */ 35