1bd063a73SJoel Goddard /* 28852fb5bSBipin Ravi * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3bd063a73SJoel Goddard * 4bd063a73SJoel Goddard * SPDX-License-Identifier: BSD-3-Clause 5bd063a73SJoel Goddard */ 6bd063a73SJoel Goddard 7bd063a73SJoel Goddard #ifndef NEOVERSE_V2_H 8bd063a73SJoel Goddard #define NEOVERSE_V2_H 9bd063a73SJoel Goddard 10bd063a73SJoel Goddard #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11bd063a73SJoel Goddard 12bd063a73SJoel Goddard /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13bd063a73SJoel Goddard #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14bd063a73SJoel Goddard 15bd063a73SJoel Goddard /******************************************************************************* 16bd063a73SJoel Goddard * CPU Extended Control register specific definitions 17bd063a73SJoel Goddard ******************************************************************************/ 18bd063a73SJoel Goddard #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 19bd063a73SJoel Goddard 20bd063a73SJoel Goddard /******************************************************************************* 21bd063a73SJoel Goddard * CPU Power Control register specific definitions 22bd063a73SJoel Goddard ******************************************************************************/ 23bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25bd063a73SJoel Goddard 268852fb5bSBipin Ravi /******************************************************************************* 278852fb5bSBipin Ravi * CPU Extended Control register 2 specific definitions. 288852fb5bSBipin Ravi ******************************************************************************/ 298852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 308852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 318852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) 328852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 338852fb5bSBipin Ravi 34b0114025SBipin Ravi /******************************************************************************* 35b0114025SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 36b0114025SBipin Ravi ******************************************************************************/ 37b0114025SBipin Ravi #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 38b0114025SBipin Ravi #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 39b0114025SBipin Ravi 40*ff342643SBipin Ravi /******************************************************************************* 41*ff342643SBipin Ravi * CPU Auxiliary Control register 3 specific definitions. 42*ff342643SBipin Ravi ******************************************************************************/ 43*ff342643SBipin Ravi #define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 44*ff342643SBipin Ravi #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 45*ff342643SBipin Ravi 46bd063a73SJoel Goddard #endif /* NEOVERSE_V2_H */ 47