1*bd063a73SJoel Goddard /* 2*bd063a73SJoel Goddard * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3*bd063a73SJoel Goddard * 4*bd063a73SJoel Goddard * SPDX-License-Identifier: BSD-3-Clause 5*bd063a73SJoel Goddard */ 6*bd063a73SJoel Goddard 7*bd063a73SJoel Goddard #ifndef NEOVERSE_V2_H 8*bd063a73SJoel Goddard #define NEOVERSE_V2_H 9*bd063a73SJoel Goddard 10*bd063a73SJoel Goddard #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11*bd063a73SJoel Goddard 12*bd063a73SJoel Goddard /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13*bd063a73SJoel Goddard #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14*bd063a73SJoel Goddard 15*bd063a73SJoel Goddard /******************************************************************************* 16*bd063a73SJoel Goddard * CPU Extended Control register specific definitions 17*bd063a73SJoel Goddard ******************************************************************************/ 18*bd063a73SJoel Goddard #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 19*bd063a73SJoel Goddard 20*bd063a73SJoel Goddard /******************************************************************************* 21*bd063a73SJoel Goddard * CPU Power Control register specific definitions 22*bd063a73SJoel Goddard ******************************************************************************/ 23*bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24*bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25*bd063a73SJoel Goddard 26*bd063a73SJoel Goddard #endif /* NEOVERSE_V2_H */ 27