xref: /rk3399_ARM-atf/include/lib/cpus/aarch64/neoverse_v2.h (revision 8852fb5b7d94229475446c81cfa58851bc2204ff)
1bd063a73SJoel Goddard /*
2*8852fb5bSBipin Ravi  * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3bd063a73SJoel Goddard  *
4bd063a73SJoel Goddard  * SPDX-License-Identifier: BSD-3-Clause
5bd063a73SJoel Goddard  */
6bd063a73SJoel Goddard 
7bd063a73SJoel Goddard #ifndef NEOVERSE_V2_H
8bd063a73SJoel Goddard #define NEOVERSE_V2_H
9bd063a73SJoel Goddard 
10bd063a73SJoel Goddard #define NEOVERSE_V2_MIDR				U(0x410FD4F0)
11bd063a73SJoel Goddard 
12bd063a73SJoel Goddard /* Neoverse V2 loop count for CVE-2022-23960 mitigation */
13bd063a73SJoel Goddard #define NEOVERSE_V2_BHB_LOOP_COUNT			U(132)
14bd063a73SJoel Goddard 
15bd063a73SJoel Goddard /*******************************************************************************
16bd063a73SJoel Goddard  * CPU Extended Control register specific definitions
17bd063a73SJoel Goddard  ******************************************************************************/
18bd063a73SJoel Goddard #define NEOVERSE_V2_CPUECTLR_EL1			S3_0_C15_C1_4
19bd063a73SJoel Goddard 
20bd063a73SJoel Goddard /*******************************************************************************
21bd063a73SJoel Goddard  * CPU Power Control register specific definitions
22bd063a73SJoel Goddard  ******************************************************************************/
23bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1			S3_0_C15_C2_7
24bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
25bd063a73SJoel Goddard 
26*8852fb5bSBipin Ravi /*******************************************************************************
27*8852fb5bSBipin Ravi  * CPU Extended Control register 2 specific definitions.
28*8852fb5bSBipin Ravi  ******************************************************************************/
29*8852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1			S3_0_C15_C1_5
30*8852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
31*8852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB		U(11)
32*8852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH		U(4)
33*8852fb5bSBipin Ravi 
34bd063a73SJoel Goddard #endif /* NEOVERSE_V2_H */
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