1bd063a73SJoel Goddard /* 256bb1d17SArvind Ram Prakash * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3bd063a73SJoel Goddard * 4bd063a73SJoel Goddard * SPDX-License-Identifier: BSD-3-Clause 5bd063a73SJoel Goddard */ 6bd063a73SJoel Goddard 7bd063a73SJoel Goddard #ifndef NEOVERSE_V2_H 8bd063a73SJoel Goddard #define NEOVERSE_V2_H 9bd063a73SJoel Goddard 10bd063a73SJoel Goddard #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11bd063a73SJoel Goddard 12bd063a73SJoel Goddard /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13bd063a73SJoel Goddard #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14bd063a73SJoel Goddard 15bd063a73SJoel Goddard /******************************************************************************* 16bd063a73SJoel Goddard * CPU Extended Control register specific definitions 17bd063a73SJoel Goddard ******************************************************************************/ 18bd063a73SJoel Goddard #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 196aa5d1b3SYounghyun Park #define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 20bd063a73SJoel Goddard 21bd063a73SJoel Goddard /******************************************************************************* 22bd063a73SJoel Goddard * CPU Power Control register specific definitions 23bd063a73SJoel Goddard ******************************************************************************/ 24bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25bd063a73SJoel Goddard #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26c0f8ce53SBipin Ravi #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT U(4) 27c0f8ce53SBipin Ravi #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH U(3) 28c0f8ce53SBipin Ravi #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT U(7) 29c0f8ce53SBipin Ravi #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH U(3) 30bd063a73SJoel Goddard 318852fb5bSBipin Ravi /******************************************************************************* 328852fb5bSBipin Ravi * CPU Extended Control register 2 specific definitions. 338852fb5bSBipin Ravi ******************************************************************************/ 348852fb5bSBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 35912c4090SBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 36912c4090SBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0) 37912c4090SBipin Ravi #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3) 388852fb5bSBipin Ravi 39b0114025SBipin Ravi /******************************************************************************* 40*7d947650SArvind Ram Prakash * CPU Auxiliary Control register specific definitions. 41*7d947650SArvind Ram Prakash ******************************************************************************/ 42*7d947650SArvind Ram Prakash #define NEOVERSE_V2_CPUACTLR_EL1 S3_0_C15_C1_0 43*7d947650SArvind Ram Prakash 44*7d947650SArvind Ram Prakash /******************************************************************************* 45b0114025SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 46b0114025SBipin Ravi ******************************************************************************/ 47b0114025SBipin Ravi #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 48b0114025SBipin Ravi #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 49b0114025SBipin Ravi 50ff342643SBipin Ravi /******************************************************************************* 51ff342643SBipin Ravi * CPU Auxiliary Control register 3 specific definitions. 52ff342643SBipin Ravi ******************************************************************************/ 53ff342643SBipin Ravi #define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 54ff342643SBipin Ravi #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 55ff342643SBipin Ravi 5658dd153cSBipin Ravi /******************************************************************************* 5758dd153cSBipin Ravi * CPU Auxiliary Control register 5 specific definitions. 5858dd153cSBipin Ravi ******************************************************************************/ 5958dd153cSBipin Ravi #define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 6058dd153cSBipin Ravi #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 6158dd153cSBipin Ravi #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 6258dd153cSBipin Ravi 6356bb1d17SArvind Ram Prakash /******************************************************************************* 6456bb1d17SArvind Ram Prakash * CPU Auxiliary control register 6 specific definitions 6556bb1d17SArvind Ram Prakash ******************************************************************************/ 6656bb1d17SArvind Ram Prakash #define NEOVERSE_V2_CPUACTLR6_EL1 S3_0_C15_C8_1 6756bb1d17SArvind Ram Prakash 68bd063a73SJoel Goddard #endif /* NEOVERSE_V2_H */ 69