1*467937b6SJimmy Brisson /* 2*467937b6SJimmy Brisson * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3*467937b6SJimmy Brisson * 4*467937b6SJimmy Brisson * SPDX-License-Identifier: BSD-3-Clause 5*467937b6SJimmy Brisson */ 6*467937b6SJimmy Brisson 7*467937b6SJimmy Brisson #ifndef NEOVERSE_V1_H 8*467937b6SJimmy Brisson #define NEOVERSE_V1_H 9*467937b6SJimmy Brisson 10*467937b6SJimmy Brisson #define NEOVERSE_V1_MIDR U(0x410FD400) 11*467937b6SJimmy Brisson 12*467937b6SJimmy Brisson /******************************************************************************* 13*467937b6SJimmy Brisson * CPU Extended Control register specific definitions. 14*467937b6SJimmy Brisson ******************************************************************************/ 15*467937b6SJimmy Brisson #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 16*467937b6SJimmy Brisson 17*467937b6SJimmy Brisson /******************************************************************************* 18*467937b6SJimmy Brisson * CPU Power Control register specific definitions 19*467937b6SJimmy Brisson ******************************************************************************/ 20*467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 22*467937b6SJimmy Brisson 23*467937b6SJimmy Brisson #endif /* NEOVERSE_V1_H */ 24