1467937b6SJimmy Brisson /* 2*33e3e925Sjohpow01 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3467937b6SJimmy Brisson * 4467937b6SJimmy Brisson * SPDX-License-Identifier: BSD-3-Clause 5467937b6SJimmy Brisson */ 6467937b6SJimmy Brisson 7467937b6SJimmy Brisson #ifndef NEOVERSE_V1_H 8467937b6SJimmy Brisson #define NEOVERSE_V1_H 9467937b6SJimmy Brisson 10467937b6SJimmy Brisson #define NEOVERSE_V1_MIDR U(0x410FD400) 11467937b6SJimmy Brisson 12467937b6SJimmy Brisson /******************************************************************************* 13467937b6SJimmy Brisson * CPU Extended Control register specific definitions. 14467937b6SJimmy Brisson ******************************************************************************/ 15467937b6SJimmy Brisson #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 16467937b6SJimmy Brisson 17467937b6SJimmy Brisson /******************************************************************************* 18467937b6SJimmy Brisson * CPU Power Control register specific definitions 19467937b6SJimmy Brisson ******************************************************************************/ 20467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 22467937b6SJimmy Brisson 23*33e3e925Sjohpow01 /******************************************************************************* 24*33e3e925Sjohpow01 * CPU Auxiliary Control register specific definitions. 25*33e3e925Sjohpow01 ******************************************************************************/ 26*33e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 27*33e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 28*33e3e925Sjohpow01 29467937b6SJimmy Brisson #endif /* NEOVERSE_V1_H */ 30