1467937b6SJimmy Brisson /* 2*1fe4a9d1SBipin Ravi * Copyright (c) 2019-2022, ARM Limited. All rights reserved. 3467937b6SJimmy Brisson * 4467937b6SJimmy Brisson * SPDX-License-Identifier: BSD-3-Clause 5467937b6SJimmy Brisson */ 6467937b6SJimmy Brisson 7467937b6SJimmy Brisson #ifndef NEOVERSE_V1_H 8467937b6SJimmy Brisson #define NEOVERSE_V1_H 9467937b6SJimmy Brisson 10467937b6SJimmy Brisson #define NEOVERSE_V1_MIDR U(0x410FD400) 11467937b6SJimmy Brisson 12*1fe4a9d1SBipin Ravi /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ 13*1fe4a9d1SBipin Ravi #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) 14*1fe4a9d1SBipin Ravi 15467937b6SJimmy Brisson /******************************************************************************* 16467937b6SJimmy Brisson * CPU Extended Control register specific definitions. 17467937b6SJimmy Brisson ******************************************************************************/ 18467937b6SJimmy Brisson #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 19741dd04cSlaurenw-arm #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 204789cf66Slaurenw-arm #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 218e140272Snayanpatel-arm #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) 228e140272Snayanpatel-arm #define CPUECTLR_EL1_PF_MODE_LSB U(6) 238e140272Snayanpatel-arm #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) 24467937b6SJimmy Brisson 25467937b6SJimmy Brisson /******************************************************************************* 26467937b6SJimmy Brisson * CPU Power Control register specific definitions 27467937b6SJimmy Brisson ******************************************************************************/ 28467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30467937b6SJimmy Brisson 3133e3e925Sjohpow01 /******************************************************************************* 3233e3e925Sjohpow01 * CPU Auxiliary Control register specific definitions. 3333e3e925Sjohpow01 ******************************************************************************/ 3433e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 3533e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 36143b1965Slaurenw-arm #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) 3733e3e925Sjohpow01 38467937b6SJimmy Brisson #endif /* NEOVERSE_V1_H */ 39