1 /* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N2_H 8 #define NEOVERSE_N2_H 9 10 /* Neoverse N2 ID register for revision r0p0 */ 11 #define NEOVERSE_N2_MIDR U(0x410FD490) 12 13 /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 14 #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Power control register 18 ******************************************************************************/ 19 #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 20 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 26 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 27 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 28 #define NEOVERSE_N2_CPUECTLR_EL1_PFDIS_BIT (ULL(1) << 15) 29 30 /******************************************************************************* 31 * CPU Auxiliary Control register specific definitions. 32 ******************************************************************************/ 33 #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 34 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 35 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 36 37 /******************************************************************************* 38 * CPU Auxiliary Control register 2 specific definitions. 39 ******************************************************************************/ 40 #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 41 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 42 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 43 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 44 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 45 46 /******************************************************************************* 47 * CPU Auxiliary Control register 3 specific definitions. 48 ******************************************************************************/ 49 #define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 50 #define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 51 52 /******************************************************************************* 53 * CPU Auxiliary Control register 5 specific definitions. 54 ******************************************************************************/ 55 #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 56 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 57 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 58 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 59 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 60 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 61 62 /******************************************************************************* 63 * CPU Auxiliary Control register specific definitions. 64 ******************************************************************************/ 65 #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 66 #define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 67 #define CPUECTLR2_EL1_TXREQ_LSB U(0) 68 #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) 69 70 #ifndef __ASSEMBLER__ 71 long check_erratum_neoverse_n2_3701773(long cpu_rev); 72 #endif /* __ASSEMBLER__ */ 73 74 #endif /* NEOVERSE_N2_H */ 75