125bbbd2dSJavier Almansa Sobrino /* 24618b2bfSBipin Ravi * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 325bbbd2dSJavier Almansa Sobrino * 425bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 525bbbd2dSJavier Almansa Sobrino */ 625bbbd2dSJavier Almansa Sobrino 725bbbd2dSJavier Almansa Sobrino #ifndef NEOVERSE_N2_H 825bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_H 925bbbd2dSJavier Almansa Sobrino 1025bbbd2dSJavier Almansa Sobrino /* Neoverse N2 ID register for revision r0p0 */ 1125bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_MIDR U(0x410FD490) 1225bbbd2dSJavier Almansa Sobrino 1325bbbd2dSJavier Almansa Sobrino /******************************************************************************* 1425bbbd2dSJavier Almansa Sobrino * CPU Power control register 1525bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 1625bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 1725bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 1825bbbd2dSJavier Almansa Sobrino 1925bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2025bbbd2dSJavier Almansa Sobrino * CPU Extended Control register specific definitions. 2125bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 2225bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 2325bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 244618b2bfSBipin Ravi #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 2525bbbd2dSJavier Almansa Sobrino 2625bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2725bbbd2dSJavier Almansa Sobrino * CPU Auxiliary Control register specific definitions. 2825bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 2965e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 3065e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 3165e04f27SBipin Ravi 3265e04f27SBipin Ravi /******************************************************************************* 3365e04f27SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 3465e04f27SBipin Ravi ******************************************************************************/ 3525bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 3625bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 3725bbbd2dSJavier Almansa Sobrino 387cfae932SBipin Ravi /******************************************************************************* 397cfae932SBipin Ravi * CPU Auxiliary Control register 5 specific definitions. 407cfae932SBipin Ravi ******************************************************************************/ 417cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 427cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 43*ef8f0c52Snayanpatel-arm 44*ef8f0c52Snayanpatel-arm /******************************************************************************* 45*ef8f0c52Snayanpatel-arm * CPU Auxiliary Control register specific definitions. 46*ef8f0c52Snayanpatel-arm ******************************************************************************/ 47*ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 48*ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 49*ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 50*ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 517cfae932SBipin Ravi 5225bbbd2dSJavier Almansa Sobrino #endif /* NEOVERSE_N2_H */ 53