125bbbd2dSJavier Almansa Sobrino /* 2*6cb8be17SBipin Ravi * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 325bbbd2dSJavier Almansa Sobrino * 425bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 525bbbd2dSJavier Almansa Sobrino */ 625bbbd2dSJavier Almansa Sobrino 725bbbd2dSJavier Almansa Sobrino #ifndef NEOVERSE_N2_H 825bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_H 925bbbd2dSJavier Almansa Sobrino 1025bbbd2dSJavier Almansa Sobrino /* Neoverse N2 ID register for revision r0p0 */ 1125bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_MIDR U(0x410FD490) 1225bbbd2dSJavier Almansa Sobrino 131fe4a9d1SBipin Ravi /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 141fe4a9d1SBipin Ravi #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 151fe4a9d1SBipin Ravi 1625bbbd2dSJavier Almansa Sobrino /******************************************************************************* 1725bbbd2dSJavier Almansa Sobrino * CPU Power control register 1825bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 1925bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 2025bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 2125bbbd2dSJavier Almansa Sobrino 2225bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2325bbbd2dSJavier Almansa Sobrino * CPU Extended Control register specific definitions. 2425bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 2525bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 2625bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 274618b2bfSBipin Ravi #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 2825bbbd2dSJavier Almansa Sobrino 2925bbbd2dSJavier Almansa Sobrino /******************************************************************************* 3025bbbd2dSJavier Almansa Sobrino * CPU Auxiliary Control register specific definitions. 3125bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 3265e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 3365e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 345819e23bSnayanpatel-arm #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 3565e04f27SBipin Ravi 3665e04f27SBipin Ravi /******************************************************************************* 3765e04f27SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 3865e04f27SBipin Ravi ******************************************************************************/ 3925bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 40e6602d4bSAkram Ahmad #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 4125bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 4243438ad1SBoyan Karatotev #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 43884d5156SDaniel Boulby #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 4425bbbd2dSJavier Almansa Sobrino 457cfae932SBipin Ravi /******************************************************************************* 4612d28067SArvind Ram Prakash * CPU Auxiliary Control register 3 specific definitions. 4712d28067SArvind Ram Prakash ******************************************************************************/ 4812d28067SArvind Ram Prakash #define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 4912d28067SArvind Ram Prakash #define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 5012d28067SArvind Ram Prakash 5112d28067SArvind Ram Prakash /******************************************************************************* 527cfae932SBipin Ravi * CPU Auxiliary Control register 5 specific definitions. 537cfae932SBipin Ravi ******************************************************************************/ 547cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 55eb44035cSArvind Ram Prakash #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 56eb44035cSArvind Ram Prakash #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 577cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 58c948185cSnayanpatel-arm #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 59603806d1Snayanpatel-arm #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 60ef8f0c52Snayanpatel-arm 61ef8f0c52Snayanpatel-arm /******************************************************************************* 62ef8f0c52Snayanpatel-arm * CPU Auxiliary Control register specific definitions. 63ef8f0c52Snayanpatel-arm ******************************************************************************/ 64ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 65ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 66ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 67ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 68*6cb8be17SBipin Ravi #define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 69*6cb8be17SBipin Ravi #define CPUECTLR2_EL1_TXREQ_LSB U(0) 70*6cb8be17SBipin Ravi #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) 717cfae932SBipin Ravi 7225bbbd2dSJavier Almansa Sobrino #endif /* NEOVERSE_N2_H */ 73