125bbbd2dSJavier Almansa Sobrino /* 225bbbd2dSJavier Almansa Sobrino * Copyright (c) 2020, Arm Limited. All rights reserved. 325bbbd2dSJavier Almansa Sobrino * 425bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 525bbbd2dSJavier Almansa Sobrino */ 625bbbd2dSJavier Almansa Sobrino 725bbbd2dSJavier Almansa Sobrino #ifndef NEOVERSE_N2_H 825bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_H 925bbbd2dSJavier Almansa Sobrino 1025bbbd2dSJavier Almansa Sobrino /* Neoverse N2 ID register for revision r0p0 */ 1125bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_MIDR U(0x410FD490) 1225bbbd2dSJavier Almansa Sobrino 1325bbbd2dSJavier Almansa Sobrino /******************************************************************************* 1425bbbd2dSJavier Almansa Sobrino * CPU Power control register 1525bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 1625bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 1725bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 1825bbbd2dSJavier Almansa Sobrino 1925bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2025bbbd2dSJavier Almansa Sobrino * CPU Extended Control register specific definitions. 2125bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 2225bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 2325bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 2425bbbd2dSJavier Almansa Sobrino 2525bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2625bbbd2dSJavier Almansa Sobrino * CPU Auxiliary Control register specific definitions. 2725bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 28*65e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 29*65e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 30*65e04f27SBipin Ravi 31*65e04f27SBipin Ravi /******************************************************************************* 32*65e04f27SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 33*65e04f27SBipin Ravi ******************************************************************************/ 3425bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 3525bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 3625bbbd2dSJavier Almansa Sobrino 3725bbbd2dSJavier Almansa Sobrino #endif /* NEOVERSE_N2_H */ 38