1*25bbbd2dSJavier Almansa Sobrino /* 2*25bbbd2dSJavier Almansa Sobrino * Copyright (c) 2020, Arm Limited. All rights reserved. 3*25bbbd2dSJavier Almansa Sobrino * 4*25bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 5*25bbbd2dSJavier Almansa Sobrino */ 6*25bbbd2dSJavier Almansa Sobrino 7*25bbbd2dSJavier Almansa Sobrino #ifndef NEOVERSE_N2_H 8*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_H 9*25bbbd2dSJavier Almansa Sobrino 10*25bbbd2dSJavier Almansa Sobrino /* Neoverse N2 ID register for revision r0p0 */ 11*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_MIDR U(0x410FD490) 12*25bbbd2dSJavier Almansa Sobrino 13*25bbbd2dSJavier Almansa Sobrino /******************************************************************************* 14*25bbbd2dSJavier Almansa Sobrino * CPU Power control register 15*25bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 16*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 17*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 18*25bbbd2dSJavier Almansa Sobrino 19*25bbbd2dSJavier Almansa Sobrino /******************************************************************************* 20*25bbbd2dSJavier Almansa Sobrino * CPU Extended Control register specific definitions. 21*25bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 22*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 23*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 24*25bbbd2dSJavier Almansa Sobrino 25*25bbbd2dSJavier Almansa Sobrino /******************************************************************************* 26*25bbbd2dSJavier Almansa Sobrino * CPU Auxiliary Control register specific definitions. 27*25bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 28*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 29*25bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 30*25bbbd2dSJavier Almansa Sobrino 31*25bbbd2dSJavier Almansa Sobrino #endif /* NEOVERSE_N2_H */ 32