125bbbd2dSJavier Almansa Sobrino /* 2*1fe4a9d1SBipin Ravi * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 325bbbd2dSJavier Almansa Sobrino * 425bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 525bbbd2dSJavier Almansa Sobrino */ 625bbbd2dSJavier Almansa Sobrino 725bbbd2dSJavier Almansa Sobrino #ifndef NEOVERSE_N2_H 825bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_H 925bbbd2dSJavier Almansa Sobrino 1025bbbd2dSJavier Almansa Sobrino /* Neoverse N2 ID register for revision r0p0 */ 1125bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_MIDR U(0x410FD490) 1225bbbd2dSJavier Almansa Sobrino 13*1fe4a9d1SBipin Ravi /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 14*1fe4a9d1SBipin Ravi #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 15*1fe4a9d1SBipin Ravi 1625bbbd2dSJavier Almansa Sobrino /******************************************************************************* 1725bbbd2dSJavier Almansa Sobrino * CPU Power control register 1825bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 1925bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 2025bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 2125bbbd2dSJavier Almansa Sobrino 2225bbbd2dSJavier Almansa Sobrino /******************************************************************************* 2325bbbd2dSJavier Almansa Sobrino * CPU Extended Control register specific definitions. 2425bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 2525bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 2625bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 274618b2bfSBipin Ravi #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 2825bbbd2dSJavier Almansa Sobrino 2925bbbd2dSJavier Almansa Sobrino /******************************************************************************* 3025bbbd2dSJavier Almansa Sobrino * CPU Auxiliary Control register specific definitions. 3125bbbd2dSJavier Almansa Sobrino ******************************************************************************/ 3265e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 3365e04f27SBipin Ravi #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 345819e23bSnayanpatel-arm #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 3565e04f27SBipin Ravi 3665e04f27SBipin Ravi /******************************************************************************* 3765e04f27SBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 3865e04f27SBipin Ravi ******************************************************************************/ 3925bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 4025bbbd2dSJavier Almansa Sobrino #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 4125bbbd2dSJavier Almansa Sobrino 427cfae932SBipin Ravi /******************************************************************************* 437cfae932SBipin Ravi * CPU Auxiliary Control register 5 specific definitions. 447cfae932SBipin Ravi ******************************************************************************/ 457cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 467cfae932SBipin Ravi #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 47c948185cSnayanpatel-arm #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 48603806d1Snayanpatel-arm #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 49ef8f0c52Snayanpatel-arm 50ef8f0c52Snayanpatel-arm /******************************************************************************* 51ef8f0c52Snayanpatel-arm * CPU Auxiliary Control register specific definitions. 52ef8f0c52Snayanpatel-arm ******************************************************************************/ 53ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 54ef8f0c52Snayanpatel-arm #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 55ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 56ef8f0c52Snayanpatel-arm #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 577cfae932SBipin Ravi 5825bbbd2dSJavier Almansa Sobrino #endif /* NEOVERSE_N2_H */ 59