1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N1_H 8 #define NEOVERSE_N1_H 9 10 #include <lib/utils_def.h> 11 12 /* Neoverse N1 MIDR for revision 0 */ 13 #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14 15 /******************************************************************************* 16 * CPU Power Control register specific definitions. 17 ******************************************************************************/ 18 #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19 20 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 21 #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 22 23 #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 24 25 #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 26 #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 27 28 /******************************************************************************* 29 * CPU Extended Control register specific definitions. 30 ******************************************************************************/ 31 #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 32 33 /******************************************************************************* 34 * CPU Auxiliary Control register specific definitions. 35 ******************************************************************************/ 36 #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 37 38 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 39 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 40 41 /* Instruction patching registers */ 42 #define CPUPSELR_EL3 S3_6_C15_C8_0 43 #define CPUPCR_EL3 S3_6_C15_C8_1 44 #define CPUPOR_EL3 S3_6_C15_C8_2 45 #define CPUPMR_EL3 S3_6_C15_C8_3 46 47 #endif /* NEOVERSE_N1_H */ 48