1b04ea14bSJohn Tsichritzis /* 2*da6d75a0SJohn Tsichritzis * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3b04ea14bSJohn Tsichritzis * 4b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5b04ea14bSJohn Tsichritzis */ 6b04ea14bSJohn Tsichritzis 7*da6d75a0SJohn Tsichritzis #ifndef NEOVERSE_N1_H 8*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_H 9b04ea14bSJohn Tsichritzis 10b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11b04ea14bSJohn Tsichritzis 12*da6d75a0SJohn Tsichritzis /* Neoverse N1 MIDR for revision 0 */ 13*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14b04ea14bSJohn Tsichritzis 15b04ea14bSJohn Tsichritzis /******************************************************************************* 16b04ea14bSJohn Tsichritzis * CPU Extended Control register specific definitions. 17b04ea14bSJohn Tsichritzis ******************************************************************************/ 18*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 20b04ea14bSJohn Tsichritzis 21*da6d75a0SJohn Tsichritzis /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 22*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 23b04ea14bSJohn Tsichritzis 24*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 25b04ea14bSJohn Tsichritzis 26*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 27*da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 28b04ea14bSJohn Tsichritzis 29b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 30b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 31b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 32b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 33b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 34b04ea14bSJohn Tsichritzis 35*da6d75a0SJohn Tsichritzis #endif /* NEOVERSE_N1_H */ 36