1*b04ea14bSJohn Tsichritzis /* 2*b04ea14bSJohn Tsichritzis * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*b04ea14bSJohn Tsichritzis * 4*b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5*b04ea14bSJohn Tsichritzis */ 6*b04ea14bSJohn Tsichritzis 7*b04ea14bSJohn Tsichritzis #ifndef CORTEX_ARES_H 8*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_H 9*b04ea14bSJohn Tsichritzis 10*b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11*b04ea14bSJohn Tsichritzis 12*b04ea14bSJohn Tsichritzis /* Cortex-ARES MIDR for revision 0 */ 13*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_MIDR U(0x410fd0c0) 14*b04ea14bSJohn Tsichritzis 15*b04ea14bSJohn Tsichritzis /******************************************************************************* 16*b04ea14bSJohn Tsichritzis * CPU Extended Control register specific definitions. 17*b04ea14bSJohn Tsichritzis ******************************************************************************/ 18*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 20*b04ea14bSJohn Tsichritzis 21*b04ea14bSJohn Tsichritzis /* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ 22*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) 23*b04ea14bSJohn Tsichritzis 24*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) 25*b04ea14bSJohn Tsichritzis 26*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_AMU_NR_COUNTERS U(5) 27*b04ea14bSJohn Tsichritzis #define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) 28*b04ea14bSJohn Tsichritzis 29*b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 30*b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 31*b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 32*b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 33*b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 34*b04ea14bSJohn Tsichritzis 35*b04ea14bSJohn Tsichritzis #endif /* CORTEX_ARES_H */ 36