1b04ea14bSJohn Tsichritzis /* 2da6d75a0SJohn Tsichritzis * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3b04ea14bSJohn Tsichritzis * 4b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5b04ea14bSJohn Tsichritzis */ 6b04ea14bSJohn Tsichritzis 7da6d75a0SJohn Tsichritzis #ifndef NEOVERSE_N1_H 8da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_H 9b04ea14bSJohn Tsichritzis 10b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11b04ea14bSJohn Tsichritzis 12da6d75a0SJohn Tsichritzis /* Neoverse N1 MIDR for revision 0 */ 13da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14b04ea14bSJohn Tsichritzis 15*80942622Slaurenw-arm /* Exception Syndrome register EC code for IC Trap */ 16*80942622Slaurenw-arm #define NEOVERSE_N1_EC_IC_TRAP U(0x1f) 17*80942622Slaurenw-arm 18b04ea14bSJohn Tsichritzis /******************************************************************************* 19632ab3ebSLouis Mayencourt * CPU Power Control register specific definitions. 20b04ea14bSJohn Tsichritzis ******************************************************************************/ 21da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22b04ea14bSJohn Tsichritzis 23da6d75a0SJohn Tsichritzis /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 24da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 25b04ea14bSJohn Tsichritzis 26da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 27b04ea14bSJohn Tsichritzis 28da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 29da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 30b04ea14bSJohn Tsichritzis 31632ab3ebSLouis Mayencourt /******************************************************************************* 32632ab3ebSLouis Mayencourt * CPU Extended Control register specific definitions. 33632ab3ebSLouis Mayencourt ******************************************************************************/ 34632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 35632ab3ebSLouis Mayencourt 369eceb020Slauwal01 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) 3711c48370Slauwal01 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 389eceb020Slauwal01 39632ab3ebSLouis Mayencourt /******************************************************************************* 40632ab3ebSLouis Mayencourt * CPU Auxiliary Control register specific definitions. 41632ab3ebSLouis Mayencourt ******************************************************************************/ 42a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 43a601afe1Slauwal01 44a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 45411f4959Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 46a601afe1Slauwal01 47632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 48632ab3ebSLouis Mayencourt 492017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 50632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 51ef5fa7d4Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 522017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 535f5d0763SAndre Przywara #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 54e34606f2Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 55e34606f2Slauwal01 56335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 57335b3c79Slauwal01 58335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 59632ab3ebSLouis Mayencourt 60b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 61b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 62b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 63b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 64b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 65b04ea14bSJohn Tsichritzis 66da6d75a0SJohn Tsichritzis #endif /* NEOVERSE_N1_H */ 67