1b04ea14bSJohn Tsichritzis /* 2da6d75a0SJohn Tsichritzis * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3b04ea14bSJohn Tsichritzis * 4b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5b04ea14bSJohn Tsichritzis */ 6b04ea14bSJohn Tsichritzis 7da6d75a0SJohn Tsichritzis #ifndef NEOVERSE_N1_H 8da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_H 9b04ea14bSJohn Tsichritzis 10b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11b04ea14bSJohn Tsichritzis 12da6d75a0SJohn Tsichritzis /* Neoverse N1 MIDR for revision 0 */ 13da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14b04ea14bSJohn Tsichritzis 15b04ea14bSJohn Tsichritzis /******************************************************************************* 16*632ab3ebSLouis Mayencourt * CPU Power Control register specific definitions. 17b04ea14bSJohn Tsichritzis ******************************************************************************/ 18da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19b04ea14bSJohn Tsichritzis 20da6d75a0SJohn Tsichritzis /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 21da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 22b04ea14bSJohn Tsichritzis 23da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 24b04ea14bSJohn Tsichritzis 25da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 26da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 27b04ea14bSJohn Tsichritzis 28*632ab3ebSLouis Mayencourt /******************************************************************************* 29*632ab3ebSLouis Mayencourt * CPU Extended Control register specific definitions. 30*632ab3ebSLouis Mayencourt ******************************************************************************/ 31*632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 32*632ab3ebSLouis Mayencourt 33*632ab3ebSLouis Mayencourt /******************************************************************************* 34*632ab3ebSLouis Mayencourt * CPU Auxiliary Control register specific definitions. 35*632ab3ebSLouis Mayencourt ******************************************************************************/ 36*632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 37*632ab3ebSLouis Mayencourt 38*632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 39*632ab3ebSLouis Mayencourt 40b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 41b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 42b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 43b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 44b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 45b04ea14bSJohn Tsichritzis 46da6d75a0SJohn Tsichritzis #endif /* NEOVERSE_N1_H */ 47