1b04ea14bSJohn Tsichritzis /* 2da6d75a0SJohn Tsichritzis * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3b04ea14bSJohn Tsichritzis * 4b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5b04ea14bSJohn Tsichritzis */ 6b04ea14bSJohn Tsichritzis 7da6d75a0SJohn Tsichritzis #ifndef NEOVERSE_N1_H 8da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_H 9b04ea14bSJohn Tsichritzis 10b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11b04ea14bSJohn Tsichritzis 12da6d75a0SJohn Tsichritzis /* Neoverse N1 MIDR for revision 0 */ 13da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14b04ea14bSJohn Tsichritzis 15b04ea14bSJohn Tsichritzis /******************************************************************************* 16632ab3ebSLouis Mayencourt * CPU Power Control register specific definitions. 17b04ea14bSJohn Tsichritzis ******************************************************************************/ 18da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19b04ea14bSJohn Tsichritzis 20da6d75a0SJohn Tsichritzis /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 21da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 22b04ea14bSJohn Tsichritzis 23da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 24b04ea14bSJohn Tsichritzis 25da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 26da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 27b04ea14bSJohn Tsichritzis 28632ab3ebSLouis Mayencourt /******************************************************************************* 29632ab3ebSLouis Mayencourt * CPU Extended Control register specific definitions. 30632ab3ebSLouis Mayencourt ******************************************************************************/ 31632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 32632ab3ebSLouis Mayencourt 339eceb020Slauwal01 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) 349eceb020Slauwal01 35632ab3ebSLouis Mayencourt /******************************************************************************* 36632ab3ebSLouis Mayencourt * CPU Auxiliary Control register specific definitions. 37632ab3ebSLouis Mayencourt ******************************************************************************/ 38a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 39a601afe1Slauwal01 40a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 41*411f4959Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 42a601afe1Slauwal01 43632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 44632ab3ebSLouis Mayencourt 452017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 46632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 47ef5fa7d4Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 482017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 495f5d0763SAndre Przywara #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 50e34606f2Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 51e34606f2Slauwal01 52335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 53335b3c79Slauwal01 54335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 55632ab3ebSLouis Mayencourt 56b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 57b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 58b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 59b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 60b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 61b04ea14bSJohn Tsichritzis 62da6d75a0SJohn Tsichritzis #endif /* NEOVERSE_N1_H */ 63