1*fd4bb0adSJohn Tsichritzis /* 2*fd4bb0adSJohn Tsichritzis * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*fd4bb0adSJohn Tsichritzis * 4*fd4bb0adSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5*fd4bb0adSJohn Tsichritzis */ 6*fd4bb0adSJohn Tsichritzis 7*fd4bb0adSJohn Tsichritzis #ifndef CORTEX_HELIOS_H 8*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_H 9*fd4bb0adSJohn Tsichritzis 10*fd4bb0adSJohn Tsichritzis #include <lib/utils_def.h> 11*fd4bb0adSJohn Tsichritzis 12*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_MIDR U(0x410FD060) 13*fd4bb0adSJohn Tsichritzis 14*fd4bb0adSJohn Tsichritzis /******************************************************************************* 15*fd4bb0adSJohn Tsichritzis * CPU Extended Control register specific definitions. 16*fd4bb0adSJohn Tsichritzis ******************************************************************************/ 17*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 18*fd4bb0adSJohn Tsichritzis 19*fd4bb0adSJohn Tsichritzis /******************************************************************************* 20*fd4bb0adSJohn Tsichritzis * CPU Auxiliary Control register specific definitions. 21*fd4bb0adSJohn Tsichritzis ******************************************************************************/ 22*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 23*fd4bb0adSJohn Tsichritzis 24*fd4bb0adSJohn Tsichritzis /******************************************************************************* 25*fd4bb0adSJohn Tsichritzis * CPU Power Control register specific definitions. 26*fd4bb0adSJohn Tsichritzis ******************************************************************************/ 27*fd4bb0adSJohn Tsichritzis 28*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29*fd4bb0adSJohn Tsichritzis #define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30*fd4bb0adSJohn Tsichritzis 31*fd4bb0adSJohn Tsichritzis #endif /* CORTEX_HELIOS_H */ 32