1fd4bb0adSJohn Tsichritzis /* 2*4c700c15SGovindraj Raja * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3fd4bb0adSJohn Tsichritzis * 4fd4bb0adSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5fd4bb0adSJohn Tsichritzis */ 6fd4bb0adSJohn Tsichritzis 711088e39SJohn Tsichritzis #ifndef NEOVERSE_E1_H 811088e39SJohn Tsichritzis #define NEOVERSE_E1_H 9fd4bb0adSJohn Tsichritzis 10fd4bb0adSJohn Tsichritzis #include <lib/utils_def.h> 11fd4bb0adSJohn Tsichritzis 12c4187c9cSJohn Tsichritzis #define NEOVERSE_E1_MIDR U(0x410FD4A0) 13fd4bb0adSJohn Tsichritzis 14fd4bb0adSJohn Tsichritzis /******************************************************************************* 15fd4bb0adSJohn Tsichritzis * CPU Extended Control register specific definitions. 16fd4bb0adSJohn Tsichritzis ******************************************************************************/ 1711088e39SJohn Tsichritzis #define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 18fd4bb0adSJohn Tsichritzis 19fd4bb0adSJohn Tsichritzis /******************************************************************************* 20fd4bb0adSJohn Tsichritzis * CPU Auxiliary Control register specific definitions. 21fd4bb0adSJohn Tsichritzis ******************************************************************************/ 2211088e39SJohn Tsichritzis #define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 23fd4bb0adSJohn Tsichritzis 24fd4bb0adSJohn Tsichritzis /******************************************************************************* 25fd4bb0adSJohn Tsichritzis * CPU Power Control register specific definitions. 26fd4bb0adSJohn Tsichritzis ******************************************************************************/ 27fd4bb0adSJohn Tsichritzis 2811088e39SJohn Tsichritzis #define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 2911088e39SJohn Tsichritzis #define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30fd4bb0adSJohn Tsichritzis 3111088e39SJohn Tsichritzis #endif /* NEOVERSE_E1_H */ 32