1 /* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef LSC25_P_CORE_H 8 #define LSC25_P_CORE_H 9 10 #define LSC25_P_CORE_MIDR U(0x410FD860) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define LSC25_P_CORE_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16 17 /******************************************************************************* 18 * CPU Power Control register specific definitions 19 ******************************************************************************/ 20 #define LSC25_P_CORE_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21 #define LSC25_P_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22 23 /******************************************************************************* 24 * SME Control registers 25 ******************************************************************************/ 26 #define LSC25_P_CORE_SVCRSM S0_3_C4_C2_3 27 #define LSC25_P_CORE_SVCRZA S0_3_C4_C4_3 28 29 #endif /* LSC25_P_CORE_H */ 30