18a677180SJohn Tsichritzis /* 2b62673c6SBoyan Karatotev * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 38a677180SJohn Tsichritzis * 48a677180SJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 58a677180SJohn Tsichritzis */ 68a677180SJohn Tsichritzis 78a677180SJohn Tsichritzis #ifndef DSU_DEF_H 88a677180SJohn Tsichritzis #define DSU_DEF_H 98a677180SJohn Tsichritzis 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 118a677180SJohn Tsichritzis 128a677180SJohn Tsichritzis /******************************************************************** 132c3b76ceSLouis Mayencourt * DSU Cluster Configuration registers definitions 148a677180SJohn Tsichritzis ********************************************************************/ 158a677180SJohn Tsichritzis #define CLUSTERCFR_EL1 S3_0_C15_C3_0 162c3b76ceSLouis Mayencourt 172c3b76ceSLouis Mayencourt #define CLUSTERCFR_ACP_SHIFT U(11) 188a677180SJohn Tsichritzis 198a677180SJohn Tsichritzis /******************************************************************** 202c3b76ceSLouis Mayencourt * DSU Cluster Main Revision ID registers definitions 218a677180SJohn Tsichritzis ********************************************************************/ 222c3b76ceSLouis Mayencourt #define CLUSTERIDR_EL1 S3_0_C15_C3_1 232c3b76ceSLouis Mayencourt 248a677180SJohn Tsichritzis #define CLUSTERIDR_REV_SHIFT U(0) 258a677180SJohn Tsichritzis #define CLUSTERIDR_REV_BITS U(4) 268a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_SHIFT U(4) 278a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_BITS U(4) 288a677180SJohn Tsichritzis 29*efc945f1SArvind Ram Prakash #define CLUSTERREVIDR_EL1 S3_0_C15_C3_2 30*efc945f1SArvind Ram Prakash 318a677180SJohn Tsichritzis /******************************************************************** 322c3b76ceSLouis Mayencourt * DSU Cluster Auxiliary Control registers definitions 332c3b76ceSLouis Mayencourt ********************************************************************/ 342c3b76ceSLouis Mayencourt #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 359fd9f1d0Sshengfei Xu #define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5 362c3b76ceSLouis Mayencourt 37*efc945f1SArvind Ram Prakash #define CLUSTERACTLR_EL1_ASSERT_CBUSY (ULL(1) << 8) 380e985d70SLouis Mayencourt #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) 397e3273e8SBipin Ravi #define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) 40*efc945f1SArvind Ram Prakash #define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY (ULL(3) << 20) 410e985d70SLouis Mayencourt 422c3b76ceSLouis Mayencourt /******************************************************************** 432c3b76ceSLouis Mayencourt * Masks applied for DSU errata workarounds 448a677180SJohn Tsichritzis ********************************************************************/ 451a74e4a8SAntonio Nino Diaz #define DSU_ERRATA_936184_MASK (U(0x3) << 15) 468a677180SJohn Tsichritzis 47b62673c6SBoyan Karatotev #define CPUCFR_EL1 S3_0_C15_C0_0 48b62673c6SBoyan Karatotev /* SCU bit of CPU Configuration Register, EL1 */ 49b62673c6SBoyan Karatotev #define SCU_SHIFT U(2) 50b62673c6SBoyan Karatotev 519fd9f1d0Sshengfei Xu #ifndef __ASSEMBLER__ 52b62673c6SBoyan Karatotev DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrctlr_el1, CLUSTERPWRCTLR_EL1); 53b62673c6SBoyan Karatotev 54b62673c6SBoyan Karatotev /* --------------------------------------------- 55b62673c6SBoyan Karatotev * controls power features of the cluster 56b62673c6SBoyan Karatotev * 1. Cache portion power not request 57b62673c6SBoyan Karatotev * 2. Disable the retention circuit 58b62673c6SBoyan Karatotev * --------------------------------------------- 59b62673c6SBoyan Karatotev */ 60b62673c6SBoyan Karatotev static inline void dsu_pwr_dwn(void) 61b62673c6SBoyan Karatotev { 62b62673c6SBoyan Karatotev write_clusterpwrctlr_el1(0); 63b62673c6SBoyan Karatotev isb(); 64b62673c6SBoyan Karatotev } 659fd9f1d0Sshengfei Xu #endif 668a677180SJohn Tsichritzis #endif /* DSU_DEF_H */ 67