18a677180SJohn Tsichritzis /* 27e3273e8SBipin Ravi * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 38a677180SJohn Tsichritzis * 48a677180SJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 58a677180SJohn Tsichritzis */ 68a677180SJohn Tsichritzis 78a677180SJohn Tsichritzis #ifndef DSU_DEF_H 88a677180SJohn Tsichritzis #define DSU_DEF_H 98a677180SJohn Tsichritzis 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 118a677180SJohn Tsichritzis 128a677180SJohn Tsichritzis /******************************************************************** 132c3b76ceSLouis Mayencourt * DSU Cluster Configuration registers definitions 148a677180SJohn Tsichritzis ********************************************************************/ 158a677180SJohn Tsichritzis #define CLUSTERCFR_EL1 S3_0_C15_C3_0 162c3b76ceSLouis Mayencourt 172c3b76ceSLouis Mayencourt #define CLUSTERCFR_ACP_SHIFT U(11) 188a677180SJohn Tsichritzis 198a677180SJohn Tsichritzis /******************************************************************** 202c3b76ceSLouis Mayencourt * DSU Cluster Main Revision ID registers definitions 218a677180SJohn Tsichritzis ********************************************************************/ 222c3b76ceSLouis Mayencourt #define CLUSTERIDR_EL1 S3_0_C15_C3_1 232c3b76ceSLouis Mayencourt 248a677180SJohn Tsichritzis #define CLUSTERIDR_REV_SHIFT U(0) 258a677180SJohn Tsichritzis #define CLUSTERIDR_REV_BITS U(4) 268a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_SHIFT U(4) 278a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_BITS U(4) 288a677180SJohn Tsichritzis 298a677180SJohn Tsichritzis /******************************************************************** 302c3b76ceSLouis Mayencourt * DSU Cluster Auxiliary Control registers definitions 312c3b76ceSLouis Mayencourt ********************************************************************/ 322c3b76ceSLouis Mayencourt #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 33*9fd9f1d0Sshengfei Xu #define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5 342c3b76ceSLouis Mayencourt 350e985d70SLouis Mayencourt #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) 367e3273e8SBipin Ravi #define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) 370e985d70SLouis Mayencourt 382c3b76ceSLouis Mayencourt /******************************************************************** 392c3b76ceSLouis Mayencourt * Masks applied for DSU errata workarounds 408a677180SJohn Tsichritzis ********************************************************************/ 411a74e4a8SAntonio Nino Diaz #define DSU_ERRATA_936184_MASK (U(0x3) << 15) 428a677180SJohn Tsichritzis 43*9fd9f1d0Sshengfei Xu #ifndef __ASSEMBLER__ 44*9fd9f1d0Sshengfei Xu void dsu_pwr_dwn(void); 45*9fd9f1d0Sshengfei Xu #endif 468a677180SJohn Tsichritzis #endif /* DSU_DEF_H */ 47