1*8a677180SJohn Tsichritzis /* 2*8a677180SJohn Tsichritzis * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*8a677180SJohn Tsichritzis * 4*8a677180SJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5*8a677180SJohn Tsichritzis */ 6*8a677180SJohn Tsichritzis 7*8a677180SJohn Tsichritzis #ifndef DSU_DEF_H 8*8a677180SJohn Tsichritzis #define DSU_DEF_H 9*8a677180SJohn Tsichritzis 10*8a677180SJohn Tsichritzis #include <utils_def.h> 11*8a677180SJohn Tsichritzis 12*8a677180SJohn Tsichritzis /******************************************************************** 13*8a677180SJohn Tsichritzis * DSU control registers definitions * 14*8a677180SJohn Tsichritzis ********************************************************************/ 15*8a677180SJohn Tsichritzis #define CLUSTERCFR_EL1 S3_0_C15_C3_0 16*8a677180SJohn Tsichritzis #define CLUSTERIDR_EL1 S3_0_C15_C3_1 17*8a677180SJohn Tsichritzis #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 18*8a677180SJohn Tsichritzis 19*8a677180SJohn Tsichritzis /******************************************************************** 20*8a677180SJohn Tsichritzis * DSU control registers bit fields * 21*8a677180SJohn Tsichritzis ********************************************************************/ 22*8a677180SJohn Tsichritzis #define CLUSTERIDR_REV_SHIFT U(0) 23*8a677180SJohn Tsichritzis #define CLUSTERIDR_REV_BITS U(4) 24*8a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_SHIFT U(4) 25*8a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_BITS U(4) 26*8a677180SJohn Tsichritzis #define CLUSTERCFR_ACP_SHIFT U(11) 27*8a677180SJohn Tsichritzis 28*8a677180SJohn Tsichritzis /******************************************************************** 29*8a677180SJohn Tsichritzis * Masks applied for DSU errata workarounds * 30*8a677180SJohn Tsichritzis ********************************************************************/ 31*8a677180SJohn Tsichritzis #define DSU_ERRATA_936184_MASK (ULL(0x3) << 15) 32*8a677180SJohn Tsichritzis 33*8a677180SJohn Tsichritzis #endif /* DSU_DEF_H */ 34