18a677180SJohn Tsichritzis /* 2*1a74e4a8SAntonio Nino Diaz * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 38a677180SJohn Tsichritzis * 48a677180SJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 58a677180SJohn Tsichritzis */ 68a677180SJohn Tsichritzis 78a677180SJohn Tsichritzis #ifndef DSU_DEF_H 88a677180SJohn Tsichritzis #define DSU_DEF_H 98a677180SJohn Tsichritzis 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 118a677180SJohn Tsichritzis 128a677180SJohn Tsichritzis /******************************************************************** 138a677180SJohn Tsichritzis * DSU control registers definitions * 148a677180SJohn Tsichritzis ********************************************************************/ 158a677180SJohn Tsichritzis #define CLUSTERCFR_EL1 S3_0_C15_C3_0 168a677180SJohn Tsichritzis #define CLUSTERIDR_EL1 S3_0_C15_C3_1 178a677180SJohn Tsichritzis #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 188a677180SJohn Tsichritzis 198a677180SJohn Tsichritzis /******************************************************************** 208a677180SJohn Tsichritzis * DSU control registers bit fields * 218a677180SJohn Tsichritzis ********************************************************************/ 228a677180SJohn Tsichritzis #define CLUSTERIDR_REV_SHIFT U(0) 238a677180SJohn Tsichritzis #define CLUSTERIDR_REV_BITS U(4) 248a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_SHIFT U(4) 258a677180SJohn Tsichritzis #define CLUSTERIDR_VAR_BITS U(4) 268a677180SJohn Tsichritzis #define CLUSTERCFR_ACP_SHIFT U(11) 278a677180SJohn Tsichritzis 288a677180SJohn Tsichritzis /******************************************************************** 298a677180SJohn Tsichritzis * Masks applied for DSU errata workarounds * 308a677180SJohn Tsichritzis ********************************************************************/ 31*1a74e4a8SAntonio Nino Diaz #define DSU_ERRATA_936184_MASK (U(0x3) << 15) 328a677180SJohn Tsichritzis 338a677180SJohn Tsichritzis #endif /* DSU_DEF_H */ 34