1*2cdc34c5SArvind Ram Prakash /* 2*2cdc34c5SArvind Ram Prakash * Copyright (c) 2025, Arm Limited. All rights reserved. 3*2cdc34c5SArvind Ram Prakash * 4*2cdc34c5SArvind Ram Prakash * SPDX-License-Identifier: BSD-3-Clause 5*2cdc34c5SArvind Ram Prakash */ 6*2cdc34c5SArvind Ram Prakash 7*2cdc34c5SArvind Ram Prakash #ifndef DIONYSUS_H 8*2cdc34c5SArvind Ram Prakash #define DIONYSUS_H 9*2cdc34c5SArvind Ram Prakash 10*2cdc34c5SArvind Ram Prakash #include <lib/utils_def.h> 11*2cdc34c5SArvind Ram Prakash 12*2cdc34c5SArvind Ram Prakash #define DIONYSUS_MIDR U(0x410FD940) 13*2cdc34c5SArvind Ram Prakash 14*2cdc34c5SArvind Ram Prakash /******************************************************************************* 15*2cdc34c5SArvind Ram Prakash * CPU Extended Control register specific definitions 16*2cdc34c5SArvind Ram Prakash ******************************************************************************/ 17*2cdc34c5SArvind Ram Prakash #define DIONYSUS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 18*2cdc34c5SArvind Ram Prakash 19*2cdc34c5SArvind Ram Prakash /******************************************************************************* 20*2cdc34c5SArvind Ram Prakash * CPU Power Control register specific definitions 21*2cdc34c5SArvind Ram Prakash ******************************************************************************/ 22*2cdc34c5SArvind Ram Prakash #define DIONYSUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 23*2cdc34c5SArvind Ram Prakash #define DIONYSUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 24*2cdc34c5SArvind Ram Prakash 25*2cdc34c5SArvind Ram Prakash #endif /* DIONYSUS_H */ 26