1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DENVER_H 8 #define DENVER_H 9 10 /* MIDR values for Denver */ 11 #define DENVER_MIDR_PN0 U(0x4E0F0000) 12 #define DENVER_MIDR_PN1 U(0x4E0F0010) 13 #define DENVER_MIDR_PN2 U(0x4E0F0020) 14 #define DENVER_MIDR_PN3 U(0x4E0F0030) 15 #define DENVER_MIDR_PN4 U(0x4E0F0040) 16 17 /* Implementer code in the MIDR register */ 18 #define DENVER_IMPL U(0x4E) 19 20 /* CPU state ids - implementation defined */ 21 #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 22 23 /* Speculative store buffering */ 24 #define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) 25 #define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) 26 27 /* Speculative memory disambiguation */ 28 #define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) 29 #define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) 30 31 /* Core power management states */ 32 #define DENVER_CPU_PMSTATE_C1 U(0x1) 33 #define DENVER_CPU_PMSTATE_C6 U(0x6) 34 #define DENVER_CPU_PMSTATE_C7 U(0x7) 35 #define DENVER_CPU_PMSTATE_MASK U(0xF) 36 37 #ifndef __ASSEMBLY__ 38 39 /* Disable Dynamic Code Optimisation */ 40 void denver_disable_dco(void); 41 42 #endif /* __ASSEMBLY__ */ 43 44 #endif /* DENVER_H */ 45