1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DENVER_H 8 #define DENVER_H 9 10 /* MIDR values for Denver */ 11 #define DENVER_MIDR_PN0 U(0x4E0F0000) 12 #define DENVER_MIDR_PN1 U(0x4E0F0010) 13 #define DENVER_MIDR_PN2 U(0x4E0F0020) 14 #define DENVER_MIDR_PN3 U(0x4E0F0030) 15 #define DENVER_MIDR_PN4 U(0x4E0F0040) 16 #define DENVER_MIDR_PN5 U(0x4E0F0050) 17 #define DENVER_MIDR_PN6 U(0x4E0F0060) 18 #define DENVER_MIDR_PN7 U(0x4E0F0070) 19 #define DENVER_MIDR_PN8 U(0x4E0F0080) 20 21 /* Implementer code in the MIDR register */ 22 #define DENVER_IMPL U(0x4E) 23 24 /* CPU state ids - implementation defined */ 25 #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 26 27 /* Speculative store buffering */ 28 #define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) 29 #define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) 30 31 /* Speculative memory disambiguation */ 32 #define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) 33 #define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) 34 35 /* Core power management states */ 36 #define DENVER_CPU_PMSTATE_C1 U(0x1) 37 #define DENVER_CPU_PMSTATE_C6 U(0x6) 38 #define DENVER_CPU_PMSTATE_C7 U(0x7) 39 #define DENVER_CPU_PMSTATE_MASK U(0xF) 40 41 /* ACTRL_ELx bits to enable dual execution*/ 42 #define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) 43 #define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) 44 #define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) 45 46 #ifndef __ASSEMBLER__ 47 48 /* Disable Dynamic Code Optimisation */ 49 void denver_disable_dco(void); 50 51 #endif /* __ASSEMBLER__ */ 52 53 #endif /* DENVER_H */ 54