13a8c55f6SVarun Wadekar /* 2*cf3ed0dcSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53a8c55f6SVarun Wadekar */ 63a8c55f6SVarun Wadekar 73a8c55f6SVarun Wadekar #ifndef __DENVER_H__ 83a8c55f6SVarun Wadekar #define __DENVER_H__ 93a8c55f6SVarun Wadekar 10e956e228SVarun Wadekar /* MIDR values for Denver */ 11030567e6SVarun Wadekar #define DENVER_MIDR_PN0 U(0x4E0F0000) 12030567e6SVarun Wadekar #define DENVER_MIDR_PN1 U(0x4E0F0010) 13030567e6SVarun Wadekar #define DENVER_MIDR_PN2 U(0x4E0F0020) 14030567e6SVarun Wadekar #define DENVER_MIDR_PN3 U(0x4E0F0030) 15030567e6SVarun Wadekar #define DENVER_MIDR_PN4 U(0x4E0F0040) 16e956e228SVarun Wadekar 17e956e228SVarun Wadekar /* Implementer code in the MIDR register */ 18030567e6SVarun Wadekar #define DENVER_IMPL U(0x4E) 193a8c55f6SVarun Wadekar 203a8c55f6SVarun Wadekar /* CPU state ids - implementation defined */ 21030567e6SVarun Wadekar #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 223a8c55f6SVarun Wadekar 23*cf3ed0dcSVarun Wadekar /* Core power management states */ 24*cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C1 U(0x1) 25*cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C6 U(0x6) 26*cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C7 U(0x7) 27*cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_MASK U(0xF) 28*cf3ed0dcSVarun Wadekar 299f1c5dd1SVarun Wadekar #ifndef __ASSEMBLY__ 309f1c5dd1SVarun Wadekar 319f1c5dd1SVarun Wadekar /* Disable Dynamic Code Optimisation */ 329f1c5dd1SVarun Wadekar void denver_disable_dco(void); 339f1c5dd1SVarun Wadekar 349f1c5dd1SVarun Wadekar #endif 359f1c5dd1SVarun Wadekar 363a8c55f6SVarun Wadekar #endif /* __DENVER_H__ */ 37