13a8c55f6SVarun Wadekar /* 2cf3ed0dcSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53a8c55f6SVarun Wadekar */ 63a8c55f6SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef DENVER_H 8c3cf06f1SAntonio Nino Diaz #define DENVER_H 93a8c55f6SVarun Wadekar 10e956e228SVarun Wadekar /* MIDR values for Denver */ 11030567e6SVarun Wadekar #define DENVER_MIDR_PN0 U(0x4E0F0000) 12030567e6SVarun Wadekar #define DENVER_MIDR_PN1 U(0x4E0F0010) 13030567e6SVarun Wadekar #define DENVER_MIDR_PN2 U(0x4E0F0020) 14030567e6SVarun Wadekar #define DENVER_MIDR_PN3 U(0x4E0F0030) 15030567e6SVarun Wadekar #define DENVER_MIDR_PN4 U(0x4E0F0040) 16*a4a9547cSAlex Van Brunt #define DENVER_MIDR_PN5 U(0x4E0F0050) 17*a4a9547cSAlex Van Brunt #define DENVER_MIDR_PN6 U(0x4E0F0060) 18*a4a9547cSAlex Van Brunt #define DENVER_MIDR_PN7 U(0x4E0F0070) 19*a4a9547cSAlex Van Brunt #define DENVER_MIDR_PN8 U(0x4E0F0080) 20e956e228SVarun Wadekar 21e956e228SVarun Wadekar /* Implementer code in the MIDR register */ 22030567e6SVarun Wadekar #define DENVER_IMPL U(0x4E) 233a8c55f6SVarun Wadekar 243a8c55f6SVarun Wadekar /* CPU state ids - implementation defined */ 25030567e6SVarun Wadekar #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 263a8c55f6SVarun Wadekar 276cf8d65fSVarun Wadekar /* Speculative store buffering */ 286cf8d65fSVarun Wadekar #define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) 296cf8d65fSVarun Wadekar #define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) 306cf8d65fSVarun Wadekar 316cf8d65fSVarun Wadekar /* Speculative memory disambiguation */ 326cf8d65fSVarun Wadekar #define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) 336cf8d65fSVarun Wadekar #define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) 346cf8d65fSVarun Wadekar 35cf3ed0dcSVarun Wadekar /* Core power management states */ 36cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C1 U(0x1) 37cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C6 U(0x6) 38cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_C7 U(0x7) 39cf3ed0dcSVarun Wadekar #define DENVER_CPU_PMSTATE_MASK U(0xF) 40cf3ed0dcSVarun Wadekar 41d55b8f6aSKalyani Chidambaram /* ACTRL_ELx bits to enable dual execution*/ 42d55b8f6aSKalyani Chidambaram #define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) 43d55b8f6aSKalyani Chidambaram #define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) 44d55b8f6aSKalyani Chidambaram #define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) 45d55b8f6aSKalyani Chidambaram 46d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 479f1c5dd1SVarun Wadekar 489f1c5dd1SVarun Wadekar /* Disable Dynamic Code Optimisation */ 499f1c5dd1SVarun Wadekar void denver_disable_dco(void); 509f1c5dd1SVarun Wadekar 51d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 529f1c5dd1SVarun Wadekar 53c3cf06f1SAntonio Nino Diaz #endif /* DENVER_H */ 54