13a8c55f6SVarun Wadekar /* 29f1c5dd1SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53a8c55f6SVarun Wadekar */ 63a8c55f6SVarun Wadekar 73a8c55f6SVarun Wadekar #ifndef __DENVER_H__ 83a8c55f6SVarun Wadekar #define __DENVER_H__ 93a8c55f6SVarun Wadekar 10e956e228SVarun Wadekar /* MIDR values for Denver */ 11e956e228SVarun Wadekar #define DENVER_MIDR_PN0 0x4E0F0000 12e956e228SVarun Wadekar #define DENVER_MIDR_PN1 0x4E0F0010 13e956e228SVarun Wadekar #define DENVER_MIDR_PN2 0x4E0F0020 14e956e228SVarun Wadekar #define DENVER_MIDR_PN3 0x4E0F0030 15e956e228SVarun Wadekar #define DENVER_MIDR_PN4 0x4E0F0040 16e956e228SVarun Wadekar 17e956e228SVarun Wadekar /* Implementer code in the MIDR register */ 18e956e228SVarun Wadekar #define DENVER_IMPL 0x4E 193a8c55f6SVarun Wadekar 203a8c55f6SVarun Wadekar /* CPU state ids - implementation defined */ 213a8c55f6SVarun Wadekar #define DENVER_CPU_STATE_POWER_DOWN 0x3 223a8c55f6SVarun Wadekar 239f1c5dd1SVarun Wadekar #ifndef __ASSEMBLY__ 249f1c5dd1SVarun Wadekar 259f1c5dd1SVarun Wadekar /* Disable Dynamic Code Optimisation */ 269f1c5dd1SVarun Wadekar void denver_disable_dco(void); 279f1c5dd1SVarun Wadekar 289f1c5dd1SVarun Wadekar #endif 299f1c5dd1SVarun Wadekar 303a8c55f6SVarun Wadekar #endif /* __DENVER_H__ */ 31