1*3a8c55f6SVarun Wadekar /* 2*3a8c55f6SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*3a8c55f6SVarun Wadekar * 4*3a8c55f6SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*3a8c55f6SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*3a8c55f6SVarun Wadekar * 7*3a8c55f6SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*3a8c55f6SVarun Wadekar * list of conditions and the following disclaimer. 9*3a8c55f6SVarun Wadekar * 10*3a8c55f6SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*3a8c55f6SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*3a8c55f6SVarun Wadekar * and/or other materials provided with the distribution. 13*3a8c55f6SVarun Wadekar * 14*3a8c55f6SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*3a8c55f6SVarun Wadekar * to endorse or promote products derived from this software without specific 16*3a8c55f6SVarun Wadekar * prior written permission. 17*3a8c55f6SVarun Wadekar * 18*3a8c55f6SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*3a8c55f6SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*3a8c55f6SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*3a8c55f6SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*3a8c55f6SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*3a8c55f6SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*3a8c55f6SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*3a8c55f6SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*3a8c55f6SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*3a8c55f6SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*3a8c55f6SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*3a8c55f6SVarun Wadekar */ 30*3a8c55f6SVarun Wadekar 31*3a8c55f6SVarun Wadekar #ifndef __DENVER_H__ 32*3a8c55f6SVarun Wadekar #define __DENVER_H__ 33*3a8c55f6SVarun Wadekar 34*3a8c55f6SVarun Wadekar /* MIDR for Denver v1.0 */ 35*3a8c55f6SVarun Wadekar #define DENVER_1_0_MIDR 0x4E0F0000 36*3a8c55f6SVarun Wadekar 37*3a8c55f6SVarun Wadekar /* CPU state ids - implementation defined */ 38*3a8c55f6SVarun Wadekar #define DENVER_CPU_STATE_POWER_DOWN 0x3 39*3a8c55f6SVarun Wadekar 40*3a8c55f6SVarun Wadekar #endif /* __DENVER_H__ */ 41