13a8c55f6SVarun Wadekar /* 2*030567e6SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53a8c55f6SVarun Wadekar */ 63a8c55f6SVarun Wadekar 73a8c55f6SVarun Wadekar #ifndef __DENVER_H__ 83a8c55f6SVarun Wadekar #define __DENVER_H__ 93a8c55f6SVarun Wadekar 10e956e228SVarun Wadekar /* MIDR values for Denver */ 11*030567e6SVarun Wadekar #define DENVER_MIDR_PN0 U(0x4E0F0000) 12*030567e6SVarun Wadekar #define DENVER_MIDR_PN1 U(0x4E0F0010) 13*030567e6SVarun Wadekar #define DENVER_MIDR_PN2 U(0x4E0F0020) 14*030567e6SVarun Wadekar #define DENVER_MIDR_PN3 U(0x4E0F0030) 15*030567e6SVarun Wadekar #define DENVER_MIDR_PN4 U(0x4E0F0040) 16e956e228SVarun Wadekar 17e956e228SVarun Wadekar /* Implementer code in the MIDR register */ 18*030567e6SVarun Wadekar #define DENVER_IMPL U(0x4E) 193a8c55f6SVarun Wadekar 203a8c55f6SVarun Wadekar /* CPU state ids - implementation defined */ 21*030567e6SVarun Wadekar #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 223a8c55f6SVarun Wadekar 239f1c5dd1SVarun Wadekar #ifndef __ASSEMBLY__ 249f1c5dd1SVarun Wadekar 259f1c5dd1SVarun Wadekar /* Disable Dynamic Code Optimisation */ 269f1c5dd1SVarun Wadekar void denver_disable_dco(void); 279f1c5dd1SVarun Wadekar 289f1c5dd1SVarun Wadekar #endif 299f1c5dd1SVarun Wadekar 303a8c55f6SVarun Wadekar #endif /* __DENVER_H__ */ 31