xref: /rk3399_ARM-atf/include/lib/cpus/aarch64/cpuamu.h (revision f06890ea89f6c20f5d4619ba3d108c43d5d89b18)
1a2e702a2SDimitris Papastamos /*
2a2e702a2SDimitris Papastamos  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3a2e702a2SDimitris Papastamos  *
4a2e702a2SDimitris Papastamos  * SPDX-License-Identifier: BSD-3-Clause
5a2e702a2SDimitris Papastamos  */
6a2e702a2SDimitris Papastamos 
7a2e702a2SDimitris Papastamos #ifndef __CPUAMU_H__
8a2e702a2SDimitris Papastamos #define __CPUAMU_H__
9a2e702a2SDimitris Papastamos 
10a2e702a2SDimitris Papastamos /*******************************************************************************
11a2e702a2SDimitris Papastamos  * CPU Activity Monitor Unit register specific definitions.
12a2e702a2SDimitris Papastamos  ******************************************************************************/
13a2e702a2SDimitris Papastamos #define CPUAMCNTENCLR_EL0	S3_3_C15_C9_7
14a2e702a2SDimitris Papastamos #define CPUAMCNTENSET_EL0	S3_3_C15_C9_6
15a2e702a2SDimitris Papastamos #define CPUAMCFGR_EL0		S3_3_C15_C10_6
16a2e702a2SDimitris Papastamos #define CPUAMUSERENR_EL0	S3_3_C15_C10_7
17a2e702a2SDimitris Papastamos 
18a2e702a2SDimitris Papastamos /* Activity Monitor Event Counter Registers */
19a2e702a2SDimitris Papastamos #define CPUAMEVCNTR0_EL0	S3_3_C15_C9_0
20a2e702a2SDimitris Papastamos #define CPUAMEVCNTR1_EL0	S3_3_C15_C9_1
21a2e702a2SDimitris Papastamos #define CPUAMEVCNTR2_EL0	S3_3_C15_C9_2
22a2e702a2SDimitris Papastamos #define CPUAMEVCNTR3_EL0	S3_3_C15_C9_3
23a2e702a2SDimitris Papastamos #define CPUAMEVCNTR4_EL0	S3_3_C15_C9_4
24a2e702a2SDimitris Papastamos 
25a2e702a2SDimitris Papastamos /* Activity Monitor Event Type Registers */
26a2e702a2SDimitris Papastamos #define CPUAMEVTYPER0_EL0	S3_3_C15_C10_0
27a2e702a2SDimitris Papastamos #define CPUAMEVTYPER1_EL0	S3_3_C15_C10_1
28a2e702a2SDimitris Papastamos #define CPUAMEVTYPER2_EL0	S3_3_C15_C10_2
29a2e702a2SDimitris Papastamos #define CPUAMEVTYPER3_EL0	S3_3_C15_C10_3
30a2e702a2SDimitris Papastamos #define CPUAMEVTYPER4_EL0	S3_3_C15_C10_4
31a2e702a2SDimitris Papastamos 
32a2e702a2SDimitris Papastamos #ifndef __ASSEMBLY__
33a2e702a2SDimitris Papastamos #include <stdint.h>
34a2e702a2SDimitris Papastamos 
35a2e702a2SDimitris Papastamos uint64_t cpuamu_cnt_read(int idx);
36a2e702a2SDimitris Papastamos void cpuamu_cnt_write(int idx, uint64_t val);
37a2e702a2SDimitris Papastamos unsigned int cpuamu_read_cpuamcntenset_el0(void);
38a2e702a2SDimitris Papastamos unsigned int cpuamu_read_cpuamcntenclr_el0(void);
39a2e702a2SDimitris Papastamos void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
40a2e702a2SDimitris Papastamos void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
41*f06890eaSDimitris Papastamos 
42*f06890eaSDimitris Papastamos int midr_match(unsigned int cpu_midr);
43*f06890eaSDimitris Papastamos void cpuamu_context_save(unsigned int nr_counters);
44*f06890eaSDimitris Papastamos void cpuamu_context_restore(unsigned int nr_counters);
45*f06890eaSDimitris Papastamos 
46a2e702a2SDimitris Papastamos #endif /* __ASSEMBLY__ */
47a2e702a2SDimitris Papastamos 
48a2e702a2SDimitris Papastamos #endif /* __CPUAMU_H__ */
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