1/* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#ifndef __CPU_MACROS_S__ 7#define __CPU_MACROS_S__ 8 9#include <arch.h> 10#include <errata_report.h> 11 12#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ 13 (MIDR_PN_MASK << MIDR_PN_SHIFT) 14 15/* The number of CPU operations allowed */ 16#define CPU_MAX_PWR_DWN_OPS 2 17 18/* Special constant to specify that CPU has no reset function */ 19#define CPU_NO_RESET_FUNC 0 20 21#define CPU_NO_EXTRA1_FUNC 0 22#define CPU_NO_EXTRA2_FUNC 0 23 24/* Word size for 64-bit CPUs */ 25#define CPU_WORD_SIZE 8 26 27#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3) 28#define IMAGE_AT_EL3 29#endif 30 31/* 32 * Whether errata status needs reporting. Errata status is printed in debug 33 * builds for both BL1 and BL31 images. 34 */ 35#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG 36# define REPORT_ERRATA 1 37#else 38# define REPORT_ERRATA 0 39#endif 40 41 42 .equ CPU_MIDR_SIZE, CPU_WORD_SIZE 43 .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE 44 .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE 45 .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE 46 .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS 47 .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE 48 .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE 49 .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE 50 .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE 51 52#ifndef IMAGE_AT_EL3 53 .equ CPU_RESET_FUNC_SIZE, 0 54#endif 55 56/* The power down core and cluster is needed only in BL31 */ 57#ifndef IMAGE_BL31 58 .equ CPU_PWR_DWN_OPS_SIZE, 0 59#endif 60 61/* Fields required to print errata status. */ 62#if !REPORT_ERRATA 63 .equ CPU_ERRATA_FUNC_SIZE, 0 64#endif 65 66/* Only BL31 requieres mutual exclusion and printed flag. */ 67#if !(REPORT_ERRATA && defined(IMAGE_BL31)) 68 .equ CPU_ERRATA_LOCK_SIZE, 0 69 .equ CPU_ERRATA_PRINTED_SIZE, 0 70#endif 71 72#if !defined(IMAGE_BL31) || !CRASH_REPORTING 73 .equ CPU_REG_DUMP_SIZE, 0 74#endif 75 76/* 77 * Define the offsets to the fields in cpu_ops structure. 78 * Every offset is defined based in the offset and size of the previous 79 * field. 80 */ 81 .equ CPU_MIDR, 0 82 .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE 83 .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE 84 .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE 85 .equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE 86 .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE 87 .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE 88 .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE 89 .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE 90 .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE 91 92 /* 93 * Write given expressions as quad words 94 * 95 * _count: 96 * Write at least _count quad words. If the given number of 97 * expressions is less than _count, repeat the last expression to 98 * fill _count quad words in total 99 * _rest: 100 * Optional list of expressions. _this is for parameter extraction 101 * only, and has no significance to the caller 102 * 103 * Invoked as: 104 * fill_constants 2, foo, bar, blah, ... 105 */ 106 .macro fill_constants _count:req, _this, _rest:vararg 107 .ifgt \_count 108 /* Write the current expression */ 109 .ifb \_this 110 .error "Nothing to fill" 111 .endif 112 .quad \_this 113 114 /* Invoke recursively for remaining expressions */ 115 .ifnb \_rest 116 fill_constants \_count-1, \_rest 117 .else 118 fill_constants \_count-1, \_this 119 .endif 120 .endif 121 .endm 122 123 /* 124 * Declare CPU operations 125 * 126 * _name: 127 * Name of the CPU for which operations are being specified 128 * _midr: 129 * Numeric value expected to read from CPU's MIDR 130 * _resetfunc: 131 * Reset function for the CPU. If there's no CPU reset function, 132 * specify CPU_NO_RESET_FUNC 133 * _extra1: 134 * This is a placeholder for future per CPU operations. Currently, 135 * some CPUs use this entry to set a test function to determine if 136 * the workaround for CVE-2017-5715 needs to be applied or not. 137 * _extra2: 138 * This is a placeholder for future per CPU operations. Currently 139 * some CPUs use this entry to set a function to disable the 140 * workaround for CVE-2018-3639. 141 * _power_down_ops: 142 * Comma-separated list of functions to perform power-down 143 * operatios on the CPU. At least one, and up to 144 * CPU_MAX_PWR_DWN_OPS number of functions may be specified. 145 * Starting at power level 0, these functions shall handle power 146 * down at subsequent power levels. If there aren't exactly 147 * CPU_MAX_PWR_DWN_OPS functions, the last specified one will be 148 * used to handle power down at subsequent levels 149 */ 150 .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ 151 _extra1:req, _extra2:req, _power_down_ops:vararg 152 .section cpu_ops, "a" 153 .align 3 154 .type cpu_ops_\_name, %object 155 .quad \_midr 156#if defined(IMAGE_AT_EL3) 157 .quad \_resetfunc 158#endif 159 .quad \_extra1 160 .quad \_extra2 161#ifdef IMAGE_BL31 162 /* Insert list of functions */ 163 fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops 164#endif 165 166#if REPORT_ERRATA 167 .ifndef \_name\()_cpu_str 168 /* 169 * Place errata reported flag, and the spinlock to arbitrate access to 170 * it in the data section. 171 */ 172 .pushsection .data 173 define_asm_spinlock \_name\()_errata_lock 174 \_name\()_errata_reported: 175 .word 0 176 .popsection 177 178 /* Place CPU string in rodata */ 179 .pushsection .rodata 180 \_name\()_cpu_str: 181 .asciz "\_name" 182 .popsection 183 .endif 184 185 /* 186 * Weakly-bound, optional errata status printing function for CPUs of 187 * this class. 188 */ 189 .weak \_name\()_errata_report 190 .quad \_name\()_errata_report 191 192#ifdef IMAGE_BL31 193 /* Pointers to errata lock and reported flag */ 194 .quad \_name\()_errata_lock 195 .quad \_name\()_errata_reported 196#endif 197#endif 198 199#if defined(IMAGE_BL31) && CRASH_REPORTING 200 .quad \_name\()_cpu_reg_dump 201#endif 202 .endm 203 204 .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ 205 _power_down_ops:vararg 206 declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \ 207 \_power_down_ops 208 .endm 209 210 .macro declare_cpu_ops_wa _name:req, _midr:req, \ 211 _resetfunc:req, _extra1:req, _extra2:req, \ 212 _power_down_ops:vararg 213 declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ 214 \_extra1, \_extra2, \_power_down_ops 215 .endm 216 217#if REPORT_ERRATA 218 /* 219 * Print status of a CPU errata 220 * 221 * _chosen: 222 * Identifier indicating whether or not a CPU errata has been 223 * compiled in. 224 * _cpu: 225 * Name of the CPU 226 * _id: 227 * Errata identifier 228 * _rev_var: 229 * Register containing the combined value CPU revision and variant 230 * - typically the return value of cpu_get_rev_var 231 */ 232 .macro report_errata _chosen, _cpu, _id, _rev_var=x8 233 /* Stash a string with errata ID */ 234 .pushsection .rodata 235 \_cpu\()_errata_\_id\()_str: 236 .asciz "\_id" 237 .popsection 238 239 /* Check whether errata applies */ 240 mov x0, \_rev_var 241 /* Shall clobber: x0-x7 */ 242 bl check_errata_\_id 243 244 .ifeq \_chosen 245 /* 246 * Errata workaround has not been compiled in. If the errata would have 247 * applied had it been compiled in, print its status as missing. 248 */ 249 cbz x0, 900f 250 mov x0, #ERRATA_MISSING 251 .endif 252900: 253 adr x1, \_cpu\()_cpu_str 254 adr x2, \_cpu\()_errata_\_id\()_str 255 bl errata_print_msg 256 .endm 257#endif 258 259#endif /* __CPU_MACROS_S__ */ 260 261 /* 262 * This macro is used on some CPUs to detect if they are vulnerable 263 * to CVE-2017-5715. 264 */ 265 .macro cpu_check_csv2 _reg _label 266 mrs \_reg, id_aa64pfr0_el1 267 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 268 /* 269 * If the field equals to 1 then branch targets trained in one 270 * context cannot affect speculative execution in a different context. 271 */ 272 cmp \_reg, #1 273 beq \_label 274 .endm 275