1/* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#ifndef CPU_MACROS_S 7#define CPU_MACROS_S 8 9#include <arch.h> 10#include <assert_macros.S> 11#include <lib/cpus/errata_report.h> 12 13#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ 14 (MIDR_PN_MASK << MIDR_PN_SHIFT) 15 16/* The number of CPU operations allowed */ 17#define CPU_MAX_PWR_DWN_OPS 2 18 19/* Special constant to specify that CPU has no reset function */ 20#define CPU_NO_RESET_FUNC 0 21 22#define CPU_NO_EXTRA1_FUNC 0 23#define CPU_NO_EXTRA2_FUNC 0 24 25/* Word size for 64-bit CPUs */ 26#define CPU_WORD_SIZE 8 27 28#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3) 29#define IMAGE_AT_EL3 30#endif 31 32/* 33 * Whether errata status needs reporting. Errata status is printed in debug 34 * builds for both BL1 and BL31 images. 35 */ 36#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG 37# define REPORT_ERRATA 1 38#else 39# define REPORT_ERRATA 0 40#endif 41 42 43 .equ CPU_MIDR_SIZE, CPU_WORD_SIZE 44 .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE 45 .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE 46 .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE 47 .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS 48 .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE 49 .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE 50 .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE 51 .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE 52 53#ifndef IMAGE_AT_EL3 54 .equ CPU_RESET_FUNC_SIZE, 0 55#endif 56 57/* The power down core and cluster is needed only in BL31 */ 58#ifndef IMAGE_BL31 59 .equ CPU_PWR_DWN_OPS_SIZE, 0 60#endif 61 62/* Fields required to print errata status. */ 63#if !REPORT_ERRATA 64 .equ CPU_ERRATA_FUNC_SIZE, 0 65#endif 66 67/* Only BL31 requieres mutual exclusion and printed flag. */ 68#if !(REPORT_ERRATA && defined(IMAGE_BL31)) 69 .equ CPU_ERRATA_LOCK_SIZE, 0 70 .equ CPU_ERRATA_PRINTED_SIZE, 0 71#endif 72 73#if !defined(IMAGE_BL31) || !CRASH_REPORTING 74 .equ CPU_REG_DUMP_SIZE, 0 75#endif 76 77/* 78 * Define the offsets to the fields in cpu_ops structure. 79 * Every offset is defined based in the offset and size of the previous 80 * field. 81 */ 82 .equ CPU_MIDR, 0 83 .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE 84 .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE 85 .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE 86 .equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE 87 .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE 88 .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE 89 .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE 90 .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE 91 .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE 92 93 /* 94 * Write given expressions as quad words 95 * 96 * _count: 97 * Write at least _count quad words. If the given number of 98 * expressions is less than _count, repeat the last expression to 99 * fill _count quad words in total 100 * _rest: 101 * Optional list of expressions. _this is for parameter extraction 102 * only, and has no significance to the caller 103 * 104 * Invoked as: 105 * fill_constants 2, foo, bar, blah, ... 106 */ 107 .macro fill_constants _count:req, _this, _rest:vararg 108 .ifgt \_count 109 /* Write the current expression */ 110 .ifb \_this 111 .error "Nothing to fill" 112 .endif 113 .quad \_this 114 115 /* Invoke recursively for remaining expressions */ 116 .ifnb \_rest 117 fill_constants \_count-1, \_rest 118 .else 119 fill_constants \_count-1, \_this 120 .endif 121 .endif 122 .endm 123 124 /* 125 * Declare CPU operations 126 * 127 * _name: 128 * Name of the CPU for which operations are being specified 129 * _midr: 130 * Numeric value expected to read from CPU's MIDR 131 * _resetfunc: 132 * Reset function for the CPU. If there's no CPU reset function, 133 * specify CPU_NO_RESET_FUNC 134 * _extra1: 135 * This is a placeholder for future per CPU operations. Currently, 136 * some CPUs use this entry to set a test function to determine if 137 * the workaround for CVE-2017-5715 needs to be applied or not. 138 * _extra2: 139 * This is a placeholder for future per CPU operations. Currently 140 * some CPUs use this entry to set a function to disable the 141 * workaround for CVE-2018-3639. 142 * _power_down_ops: 143 * Comma-separated list of functions to perform power-down 144 * operatios on the CPU. At least one, and up to 145 * CPU_MAX_PWR_DWN_OPS number of functions may be specified. 146 * Starting at power level 0, these functions shall handle power 147 * down at subsequent power levels. If there aren't exactly 148 * CPU_MAX_PWR_DWN_OPS functions, the last specified one will be 149 * used to handle power down at subsequent levels 150 */ 151 .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ 152 _extra1:req, _extra2:req, _power_down_ops:vararg 153 .section cpu_ops, "a" 154 .align 3 155 .type cpu_ops_\_name, %object 156 .quad \_midr 157#if defined(IMAGE_AT_EL3) 158 .quad \_resetfunc 159#endif 160 .quad \_extra1 161 .quad \_extra2 162#ifdef IMAGE_BL31 163 /* Insert list of functions */ 164 fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops 165#endif 166 167#if REPORT_ERRATA 168 .ifndef \_name\()_cpu_str 169 /* 170 * Place errata reported flag, and the spinlock to arbitrate access to 171 * it in the data section. 172 */ 173 .pushsection .data 174 define_asm_spinlock \_name\()_errata_lock 175 \_name\()_errata_reported: 176 .word 0 177 .popsection 178 179 /* Place CPU string in rodata */ 180 .pushsection .rodata 181 \_name\()_cpu_str: 182 .asciz "\_name" 183 .popsection 184 .endif 185 186 /* 187 * Mandatory errata status printing function for CPUs of 188 * this class. 189 */ 190 .quad \_name\()_errata_report 191 192#ifdef IMAGE_BL31 193 /* Pointers to errata lock and reported flag */ 194 .quad \_name\()_errata_lock 195 .quad \_name\()_errata_reported 196#endif 197#endif 198 199#if defined(IMAGE_BL31) && CRASH_REPORTING 200 .quad \_name\()_cpu_reg_dump 201#endif 202 .endm 203 204 .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ 205 _power_down_ops:vararg 206 declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \ 207 \_power_down_ops 208 .endm 209 210 .macro declare_cpu_ops_wa _name:req, _midr:req, \ 211 _resetfunc:req, _extra1:req, _extra2:req, \ 212 _power_down_ops:vararg 213 declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ 214 \_extra1, \_extra2, \_power_down_ops 215 .endm 216 217#if REPORT_ERRATA 218 /* 219 * Print status of a CPU errata 220 * 221 * _chosen: 222 * Identifier indicating whether or not a CPU errata has been 223 * compiled in. 224 * _cpu: 225 * Name of the CPU 226 * _id: 227 * Errata identifier 228 * _rev_var: 229 * Register containing the combined value CPU revision and variant 230 * - typically the return value of cpu_get_rev_var 231 */ 232 .macro report_errata _chosen, _cpu, _id, _rev_var=x8 233 /* Stash a string with errata ID */ 234 .pushsection .rodata 235 \_cpu\()_errata_\_id\()_str: 236 .asciz "\_id" 237 .popsection 238 239 /* Check whether errata applies */ 240 mov x0, \_rev_var 241 /* Shall clobber: x0-x7 */ 242 bl check_errata_\_id 243 244 .ifeq \_chosen 245 /* 246 * Errata workaround has not been compiled in. If the errata would have 247 * applied had it been compiled in, print its status as missing. 248 */ 249 cbz x0, 900f 250 mov x0, #ERRATA_MISSING 251 .endif 252900: 253 adr x1, \_cpu\()_cpu_str 254 adr x2, \_cpu\()_errata_\_id\()_str 255 bl errata_print_msg 256 .endm 257#endif 258 259 /* 260 * This macro is used on some CPUs to detect if they are vulnerable 261 * to CVE-2017-5715. 262 */ 263 .macro cpu_check_csv2 _reg _label 264 mrs \_reg, id_aa64pfr0_el1 265 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 266 /* 267 * If the field equals 1, branch targets trained in one context cannot 268 * affect speculative execution in a different context. 269 * 270 * If the field equals 2, it means that the system is also aware of 271 * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we 272 * expect users of the registers to do the right thing. 273 * 274 * Only apply mitigations if the value of this field is 0. 275 */ 276#if ENABLE_ASSERTIONS 277 cmp \_reg, #3 /* Only values 0 to 2 are expected */ 278 ASM_ASSERT(lo) 279#endif 280 281 cmp \_reg, #0 282 bne \_label 283 .endm 284 285 /* 286 * Helper macro that reads the part number of the current 287 * CPU and jumps to the given label if it matches the CPU 288 * MIDR provided. 289 * 290 * Clobbers x0. 291 */ 292 .macro jump_if_cpu_midr _cpu_midr, _label 293 mrs x0, midr_el1 294 ubfx x0, x0, MIDR_PN_SHIFT, #12 295 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 296 b.eq \_label 297 .endm 298 299#endif /* CPU_MACROS_S */ 300