1add40351SSoby Mathew/* 210bcd761SJeenu Viswambharan * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3add40351SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5add40351SSoby Mathew */ 6e2bf57f8SDan Handley#ifndef __CPU_MACROS_S__ 7e2bf57f8SDan Handley#define __CPU_MACROS_S__ 8add40351SSoby Mathew 9add40351SSoby Mathew#include <arch.h> 1010bcd761SJeenu Viswambharan#include <errata_report.h> 11add40351SSoby Mathew 12add40351SSoby Mathew#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ 13add40351SSoby Mathew (MIDR_PN_MASK << MIDR_PN_SHIFT) 14add40351SSoby Mathew 155dd9dbb5SJeenu Viswambharan/* The number of CPU operations allowed */ 165dd9dbb5SJeenu Viswambharan#define CPU_MAX_PWR_DWN_OPS 2 175dd9dbb5SJeenu Viswambharan 185dd9dbb5SJeenu Viswambharan/* Special constant to specify that CPU has no reset function */ 195dd9dbb5SJeenu Viswambharan#define CPU_NO_RESET_FUNC 0 205dd9dbb5SJeenu Viswambharan 215dd9dbb5SJeenu Viswambharan/* Word size for 64-bit CPUs */ 225dd9dbb5SJeenu Viswambharan#define CPU_WORD_SIZE 8 235dd9dbb5SJeenu Viswambharan 24b1d27b48SRoberto Vargas#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3) 25b1d27b48SRoberto Vargas#define IMAGE_AT_EL3 26b1d27b48SRoberto Vargas#endif 27b1d27b48SRoberto Vargas 28add40351SSoby Mathew/* 2910bcd761SJeenu Viswambharan * Whether errata status needs reporting. Errata status is printed in debug 3010bcd761SJeenu Viswambharan * builds for both BL1 and BL31 images. 3110bcd761SJeenu Viswambharan */ 3210bcd761SJeenu Viswambharan#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG 3310bcd761SJeenu Viswambharan# define REPORT_ERRATA 1 3410bcd761SJeenu Viswambharan#else 3510bcd761SJeenu Viswambharan# define REPORT_ERRATA 0 3610bcd761SJeenu Viswambharan#endif 3710bcd761SJeenu Viswambharan 3810bcd761SJeenu Viswambharan /* 39add40351SSoby Mathew * Define the offsets to the fields in cpu_ops structure. 40add40351SSoby Mathew */ 41add40351SSoby Mathew .struct 0 42add40351SSoby MathewCPU_MIDR: /* cpu_ops midr */ 43add40351SSoby Mathew .space 8 44add40351SSoby Mathew/* Reset fn is needed in BL at reset vector */ 45b1d27b48SRoberto Vargas#if defined(IMAGE_AT_EL3) 46add40351SSoby MathewCPU_RESET_FUNC: /* cpu_ops reset_func */ 47add40351SSoby Mathew .space 8 48add40351SSoby Mathew#endif 493d8256b2SMasahiro Yamada#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ 505dd9dbb5SJeenu ViswambharanCPU_PWR_DWN_OPS: /* cpu_ops power down functions */ 515dd9dbb5SJeenu Viswambharan .space (8 * CPU_MAX_PWR_DWN_OPS) 52add40351SSoby Mathew#endif 5310bcd761SJeenu Viswambharan 5410bcd761SJeenu Viswambharan/* 5510bcd761SJeenu Viswambharan * Fields required to print errata status. Only in BL31 that the printing 5610bcd761SJeenu Viswambharan * require mutual exclusion and printed flag. 5710bcd761SJeenu Viswambharan */ 5810bcd761SJeenu Viswambharan#if REPORT_ERRATA 5910bcd761SJeenu ViswambharanCPU_ERRATA_FUNC: 6010bcd761SJeenu Viswambharan .space 8 61b1d27b48SRoberto Vargas#if defined(IMAGE_BL31) 6210bcd761SJeenu ViswambharanCPU_ERRATA_LOCK: 6310bcd761SJeenu Viswambharan .space 8 6410bcd761SJeenu ViswambharanCPU_ERRATA_PRINTED: 6510bcd761SJeenu Viswambharan .space 8 6610bcd761SJeenu Viswambharan#endif 6710bcd761SJeenu Viswambharan#endif 6810bcd761SJeenu Viswambharan 693d8256b2SMasahiro Yamada#if defined(IMAGE_BL31) && CRASH_REPORTING 70d3f70af6SSoby MathewCPU_REG_DUMP: /* cpu specific register dump for crash reporting */ 71d3f70af6SSoby Mathew .space 8 72d3f70af6SSoby Mathew#endif 73add40351SSoby MathewCPU_OPS_SIZE = . 74add40351SSoby Mathew 75add40351SSoby Mathew /* 765dd9dbb5SJeenu Viswambharan * Write given expressions as quad words 775dd9dbb5SJeenu Viswambharan * 785dd9dbb5SJeenu Viswambharan * _count: 795dd9dbb5SJeenu Viswambharan * Write at least _count quad words. If the given number of 805dd9dbb5SJeenu Viswambharan * expressions is less than _count, repeat the last expression to 815dd9dbb5SJeenu Viswambharan * fill _count quad words in total 825dd9dbb5SJeenu Viswambharan * _rest: 835dd9dbb5SJeenu Viswambharan * Optional list of expressions. _this is for parameter extraction 845dd9dbb5SJeenu Viswambharan * only, and has no significance to the caller 855dd9dbb5SJeenu Viswambharan * 865dd9dbb5SJeenu Viswambharan * Invoked as: 875dd9dbb5SJeenu Viswambharan * fill_constants 2, foo, bar, blah, ... 88add40351SSoby Mathew */ 895dd9dbb5SJeenu Viswambharan .macro fill_constants _count:req, _this, _rest:vararg 905dd9dbb5SJeenu Viswambharan .ifgt \_count 915dd9dbb5SJeenu Viswambharan /* Write the current expression */ 925dd9dbb5SJeenu Viswambharan .ifb \_this 935dd9dbb5SJeenu Viswambharan .error "Nothing to fill" 945dd9dbb5SJeenu Viswambharan .endif 955dd9dbb5SJeenu Viswambharan .quad \_this 965dd9dbb5SJeenu Viswambharan 975dd9dbb5SJeenu Viswambharan /* Invoke recursively for remaining expressions */ 985dd9dbb5SJeenu Viswambharan .ifnb \_rest 995dd9dbb5SJeenu Viswambharan fill_constants \_count-1, \_rest 1005dd9dbb5SJeenu Viswambharan .else 1015dd9dbb5SJeenu Viswambharan fill_constants \_count-1, \_this 1025dd9dbb5SJeenu Viswambharan .endif 1035dd9dbb5SJeenu Viswambharan .endif 1045dd9dbb5SJeenu Viswambharan .endm 1055dd9dbb5SJeenu Viswambharan 1065dd9dbb5SJeenu Viswambharan /* 1075dd9dbb5SJeenu Viswambharan * Declare CPU operations 1085dd9dbb5SJeenu Viswambharan * 1095dd9dbb5SJeenu Viswambharan * _name: 1105dd9dbb5SJeenu Viswambharan * Name of the CPU for which operations are being specified 1115dd9dbb5SJeenu Viswambharan * _midr: 1125dd9dbb5SJeenu Viswambharan * Numeric value expected to read from CPU's MIDR 1135dd9dbb5SJeenu Viswambharan * _resetfunc: 1145dd9dbb5SJeenu Viswambharan * Reset function for the CPU. If there's no CPU reset function, 1155dd9dbb5SJeenu Viswambharan * specify CPU_NO_RESET_FUNC 1165dd9dbb5SJeenu Viswambharan * _power_down_ops: 1175dd9dbb5SJeenu Viswambharan * Comma-separated list of functions to perform power-down 1185dd9dbb5SJeenu Viswambharan * operatios on the CPU. At least one, and up to 1195dd9dbb5SJeenu Viswambharan * CPU_MAX_PWR_DWN_OPS number of functions may be specified. 1205dd9dbb5SJeenu Viswambharan * Starting at power level 0, these functions shall handle power 1215dd9dbb5SJeenu Viswambharan * down at subsequent power levels. If there aren't exactly 1225dd9dbb5SJeenu Viswambharan * CPU_MAX_PWR_DWN_OPS functions, the last specified one will be 1235dd9dbb5SJeenu Viswambharan * used to handle power down at subsequent levels 1245dd9dbb5SJeenu Viswambharan */ 1255dd9dbb5SJeenu Viswambharan .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ 1265dd9dbb5SJeenu Viswambharan _power_down_ops:vararg 1275dd9dbb5SJeenu Viswambharan .section cpu_ops, "a" 1285dd9dbb5SJeenu Viswambharan .align 3 129add40351SSoby Mathew .type cpu_ops_\_name, %object 130add40351SSoby Mathew .quad \_midr 131b1d27b48SRoberto Vargas#if defined(IMAGE_AT_EL3) 1325dd9dbb5SJeenu Viswambharan .quad \_resetfunc 133add40351SSoby Mathew#endif 1343d8256b2SMasahiro Yamada#ifdef IMAGE_BL31 1355dd9dbb5SJeenu Viswambharan1: 1365dd9dbb5SJeenu Viswambharan /* Insert list of functions */ 1375dd9dbb5SJeenu Viswambharan fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops 1385dd9dbb5SJeenu Viswambharan2: 1395dd9dbb5SJeenu Viswambharan /* 1405dd9dbb5SJeenu Viswambharan * Error if no or more than CPU_MAX_PWR_DWN_OPS were specified in the 1415dd9dbb5SJeenu Viswambharan * list 1425dd9dbb5SJeenu Viswambharan */ 1435dd9dbb5SJeenu Viswambharan .ifeq 2b - 1b 1445dd9dbb5SJeenu Viswambharan .error "At least one power down function must be specified" 1455dd9dbb5SJeenu Viswambharan .else 1465dd9dbb5SJeenu Viswambharan .iflt 2b - 1b - (CPU_MAX_PWR_DWN_OPS * CPU_WORD_SIZE) 1475dd9dbb5SJeenu Viswambharan .error "More than CPU_MAX_PWR_DWN_OPS functions specified" 1485dd9dbb5SJeenu Viswambharan .endif 1495dd9dbb5SJeenu Viswambharan .endif 150add40351SSoby Mathew#endif 15110bcd761SJeenu Viswambharan 15210bcd761SJeenu Viswambharan#if REPORT_ERRATA 15310bcd761SJeenu Viswambharan .ifndef \_name\()_cpu_str 15410bcd761SJeenu Viswambharan /* 15510bcd761SJeenu Viswambharan * Place errata reported flag, and the spinlock to arbitrate access to 15610bcd761SJeenu Viswambharan * it in the data section. 15710bcd761SJeenu Viswambharan */ 15810bcd761SJeenu Viswambharan .pushsection .data 15910bcd761SJeenu Viswambharan define_asm_spinlock \_name\()_errata_lock 16010bcd761SJeenu Viswambharan \_name\()_errata_reported: 16110bcd761SJeenu Viswambharan .word 0 16210bcd761SJeenu Viswambharan .popsection 16310bcd761SJeenu Viswambharan 16410bcd761SJeenu Viswambharan /* Place CPU string in rodata */ 16510bcd761SJeenu Viswambharan .pushsection .rodata 16610bcd761SJeenu Viswambharan \_name\()_cpu_str: 16710bcd761SJeenu Viswambharan .asciz "\_name" 16810bcd761SJeenu Viswambharan .popsection 16910bcd761SJeenu Viswambharan .endif 17010bcd761SJeenu Viswambharan 17110bcd761SJeenu Viswambharan /* 17210bcd761SJeenu Viswambharan * Weakly-bound, optional errata status printing function for CPUs of 17310bcd761SJeenu Viswambharan * this class. 17410bcd761SJeenu Viswambharan */ 17510bcd761SJeenu Viswambharan .weak \_name\()_errata_report 17610bcd761SJeenu Viswambharan .quad \_name\()_errata_report 17710bcd761SJeenu Viswambharan 17810bcd761SJeenu Viswambharan#ifdef IMAGE_BL31 17910bcd761SJeenu Viswambharan /* Pointers to errata lock and reported flag */ 18010bcd761SJeenu Viswambharan .quad \_name\()_errata_lock 18110bcd761SJeenu Viswambharan .quad \_name\()_errata_reported 18210bcd761SJeenu Viswambharan#endif 18310bcd761SJeenu Viswambharan#endif 18410bcd761SJeenu Viswambharan 1853d8256b2SMasahiro Yamada#if defined(IMAGE_BL31) && CRASH_REPORTING 186d3f70af6SSoby Mathew .quad \_name\()_cpu_reg_dump 187d3f70af6SSoby Mathew#endif 188add40351SSoby Mathew .endm 189e2bf57f8SDan Handley 19010bcd761SJeenu Viswambharan#if REPORT_ERRATA 19110bcd761SJeenu Viswambharan /* 19210bcd761SJeenu Viswambharan * Print status of a CPU errata 19310bcd761SJeenu Viswambharan * 19410bcd761SJeenu Viswambharan * _chosen: 19510bcd761SJeenu Viswambharan * Identifier indicating whether or not a CPU errata has been 19610bcd761SJeenu Viswambharan * compiled in. 19710bcd761SJeenu Viswambharan * _cpu: 19810bcd761SJeenu Viswambharan * Name of the CPU 19910bcd761SJeenu Viswambharan * _id: 20010bcd761SJeenu Viswambharan * Errata identifier 20110bcd761SJeenu Viswambharan * _rev_var: 20210bcd761SJeenu Viswambharan * Register containing the combined value CPU revision and variant 20310bcd761SJeenu Viswambharan * - typically the return value of cpu_get_rev_var 20410bcd761SJeenu Viswambharan */ 20510bcd761SJeenu Viswambharan .macro report_errata _chosen, _cpu, _id, _rev_var=x8 20610bcd761SJeenu Viswambharan /* Stash a string with errata ID */ 20710bcd761SJeenu Viswambharan .pushsection .rodata 20810bcd761SJeenu Viswambharan \_cpu\()_errata_\_id\()_str: 20910bcd761SJeenu Viswambharan .asciz "\_id" 21010bcd761SJeenu Viswambharan .popsection 21110bcd761SJeenu Viswambharan 21210bcd761SJeenu Viswambharan /* Check whether errata applies */ 21310bcd761SJeenu Viswambharan mov x0, \_rev_var 21410bcd761SJeenu Viswambharan bl check_errata_\_id 21510bcd761SJeenu Viswambharan 21610bcd761SJeenu Viswambharan .ifeq \_chosen 21710bcd761SJeenu Viswambharan /* 21810bcd761SJeenu Viswambharan * Errata workaround has not been compiled in. If the errata would have 21910bcd761SJeenu Viswambharan * applied had it been compiled in, print its status as missing. 22010bcd761SJeenu Viswambharan */ 22110bcd761SJeenu Viswambharan cbz x0, 900f 22210bcd761SJeenu Viswambharan mov x0, #ERRATA_MISSING 22310bcd761SJeenu Viswambharan .endif 22410bcd761SJeenu Viswambharan900: 22510bcd761SJeenu Viswambharan adr x1, \_cpu\()_cpu_str 22610bcd761SJeenu Viswambharan adr x2, \_cpu\()_errata_\_id\()_str 22710bcd761SJeenu Viswambharan bl errata_print_msg 22810bcd761SJeenu Viswambharan .endm 22910bcd761SJeenu Viswambharan#endif 23010bcd761SJeenu Viswambharan 231e2bf57f8SDan Handley#endif /* __CPU_MACROS_S__ */ 232*3991a6a4SDimitris Papastamos 233*3991a6a4SDimitris Papastamos /* 234*3991a6a4SDimitris Papastamos * This macro is used on some CPUs to detect if they are vulnerable 235*3991a6a4SDimitris Papastamos * to CVE-2017-5715. 236*3991a6a4SDimitris Papastamos */ 237*3991a6a4SDimitris Papastamos .macro cpu_check_csv2 _reg _label 238*3991a6a4SDimitris Papastamos mrs \_reg, id_aa64pfr0_el1 239*3991a6a4SDimitris Papastamos ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 240*3991a6a4SDimitris Papastamos /* 241*3991a6a4SDimitris Papastamos * If the field equals to 1 then branch targets trained in one 242*3991a6a4SDimitris Papastamos * context cannot affect speculative execution in a different context. 243*3991a6a4SDimitris Papastamos */ 244*3991a6a4SDimitris Papastamos cmp \_reg, #1 245*3991a6a4SDimitris Papastamos beq \_label 246*3991a6a4SDimitris Papastamos .endm 247