1 /* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X4_H 8 #define CORTEX_X4_H 9 10 #define CORTEX_X4_MIDR U(0x410FD821) 11 12 /* Cortex X4 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X4_BHB_LOOP_COUNT U(132) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 19 20 /******************************************************************************* 21 * CPU Power Control register specific definitions 22 ******************************************************************************/ 23 #define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24 #define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25 26 /******************************************************************************* 27 * CPU Auxiliary control register specific definitions 28 ******************************************************************************/ 29 #define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0 30 #define CORTEX_X4_CPUACTLR2_EL1 S3_0_C15_C1_1 31 #define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2 32 #define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3 33 34 /******************************************************************************* 35 * CPU Auxiliary control register 5 specific definitions 36 ******************************************************************************/ 37 #define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0 38 #define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14) 39 40 /******************************************************************************* 41 * CPU Auxiliary control register 6 specific definitions 42 ******************************************************************************/ 43 #define CORTEX_X4_CPUACTLR6_EL1 S3_0_C15_C8_1 44 45 #ifndef __ASSEMBLER__ 46 #if ERRATA_X4_2726228 47 long check_erratum_cortex_x4_2726228(long cpu_rev); 48 #else 49 static inline long check_erratum_cortex_x4_2726228(long cpu_rev) 50 { 51 return 0; 52 } 53 #endif /* ERRATA_X4_2726228 */ 54 55 long check_erratum_cortex_x4_3701758(long cpu_rev); 56 #endif /* __ASSEMBLER__ */ 57 58 #endif /* CORTEX_X4_H */ 59