1 /* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X4_H 8 #define CORTEX_X4_H 9 10 #define CORTEX_X4_MIDR U(0x410FD821) 11 12 /* Cortex X4 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X4_BHB_LOOP_COUNT U(132) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 19 20 /******************************************************************************* 21 * CPU Power Control register specific definitions 22 ******************************************************************************/ 23 #define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24 #define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25 26 /******************************************************************************* 27 * CPU Auxiliary control register specific definitions 28 ******************************************************************************/ 29 #define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2 30 #define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3 31 32 /******************************************************************************* 33 * CPU Auxiliary control register 5 specific definitions 34 ******************************************************************************/ 35 #define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0 36 #define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14) 37 38 #ifndef __ASSEMBLER__ 39 #if ERRATA_X4_2726228 40 long check_erratum_cortex_x4_2726228(long cpu_rev); 41 #else 42 static inline long check_erratum_cortex_x4_2726228(long cpu_rev) 43 { 44 return 0; 45 } 46 #endif /* ERRATA_X4_2726228 */ 47 #endif /* __ASSEMBLER__ */ 48 49 #endif /* CORTEX_X4_H */ 50