1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X3_H 8 #define CORTEX_X3_H 9 10 #define CORTEX_X3_MIDR U(0x410FD4E0) 11 12 /* Cortex-X3 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X3_BHB_LOOP_COUNT U(132) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 19 20 /******************************************************************************* 21 * CPU Power Control register specific definitions 22 ******************************************************************************/ 23 #define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24 #define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25 #define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) 26 #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) 27 28 /******************************************************************************* 29 * CPU Auxiliary Control register 2 specific definitions. 30 ******************************************************************************/ 31 #define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 32 #define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 33 34 /******************************************************************************* 35 * CPU Auxiliary Control register 5 specific definitions. 36 ******************************************************************************/ 37 #define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 38 #define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 39 #define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 40 41 /******************************************************************************* 42 * CPU Extended Control register 2 specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 45 46 #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) 47 #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 48 #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 49 50 /******************************************************************************* 51 * CPU Auxiliary Control register 3 specific definitions. 52 ******************************************************************************/ 53 #define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2 54 #define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 55 56 #endif /* CORTEX_X3_H */ 57