16e8eca78SOkash Khawaja /* 26e8eca78SOkash Khawaja * Copyright (c) 2022, Google LLC. All rights reserved. 36e8eca78SOkash Khawaja * 46e8eca78SOkash Khawaja * SPDX-License-Identifier: BSD-3-Clause 56e8eca78SOkash Khawaja */ 66e8eca78SOkash Khawaja 76e8eca78SOkash Khawaja #ifndef CORTEX_X1_H 86e8eca78SOkash Khawaja #define CORTEX_X1_H 96e8eca78SOkash Khawaja 106e8eca78SOkash Khawaja /* Cortex-X1 MIDR for r1p0 */ 116e8eca78SOkash Khawaja #define CORTEX_X1_MIDR U(0x411fd440) 126e8eca78SOkash Khawaja 13*e81e999bSOkash Khawaja /* Cortex-X1 loop count for CVE-2022-23960 mitigation */ 14*e81e999bSOkash Khawaja #define CORTEX_X1_BHB_LOOP_COUNT U(32) 15*e81e999bSOkash Khawaja 166e8eca78SOkash Khawaja /******************************************************************************* 176e8eca78SOkash Khawaja * CPU Extended Control register specific definitions. 186e8eca78SOkash Khawaja ******************************************************************************/ 196e8eca78SOkash Khawaja #define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 206e8eca78SOkash Khawaja 216e8eca78SOkash Khawaja /******************************************************************************* 227b76c20dSOkash Khawaja * CPU Auxiliary Control register specific definitions. 237b76c20dSOkash Khawaja ******************************************************************************/ 247b76c20dSOkash Khawaja #define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1 257b76c20dSOkash Khawaja 267b76c20dSOkash Khawaja /******************************************************************************* 276e8eca78SOkash Khawaja * CPU Power Control register specific definitions 286e8eca78SOkash Khawaja ******************************************************************************/ 296e8eca78SOkash Khawaja #define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 306e8eca78SOkash Khawaja #define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1) 316e8eca78SOkash Khawaja 326e8eca78SOkash Khawaja #endif /* CORTEX_X1_H */ 33