1 /* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A78_H 8 #define CORTEX_A78_H 9 10 #include <lib/utils_def.h> 11 12 #define CORTEX_A78_MIDR U(0x410FD410) 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 18 19 /******************************************************************************* 20 * CPU Power Control register specific definitions 21 ******************************************************************************/ 22 #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 23 #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 24 25 /******************************************************************************* 26 * CPU Auxiliary Control register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) 29 30 #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 31 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) 32 33 /******************************************************************************* 34 * CPU Activity Monitor Unit register specific definitions. 35 ******************************************************************************/ 36 #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 37 #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 38 #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 39 #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 40 41 #define CORTEX_A78_AMU_GROUP0_MASK U(0xF) 42 #define CORTEX_A78_AMU_GROUP1_MASK U(0x7) 43 44 #endif /* CORTEX_A78_H */ 45