1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A76_H 8 #define CORTEX_A76_H 9 10 /* Cortex-A76 MIDR for revision 0 */ 11 #define CORTEX_A76_MIDR 0x410fd0b0 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 17 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 18 19 /******************************************************************************* 20 * CPU Auxiliary Control register specific definitions. 21 ******************************************************************************/ 22 #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 23 24 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (1 << 16) 25 26 /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ 27 #define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1 28 29 #endif /* CORTEX_A76_H */ 30