1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A75_H__ 8 #define __CORTEX_A75_H__ 9 10 /* Cortex-A75 MIDR */ 11 #define CORTEX_A75_MIDR 0x410fd0a0 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 17 #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 18 19 /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ 20 #define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 21 22 #define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) 23 24 /* 25 * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are 26 * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are 27 * programmable by programming the appropriate Event count bits in 28 * CPUAMEVTYPER<n> register and are disabled by default. Platforms may 29 * enable this with suitable programming. 30 */ 31 #define CORTEX_A75_AMU_NR_COUNTERS U(5) 32 #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) 33 #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) 34 35 #ifndef __ASSEMBLY__ 36 #include <stdint.h> 37 38 uint64_t cortex_a75_amu_cnt_read(int idx); 39 void cortex_a75_amu_cnt_write(int idx, uint64_t val); 40 unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); 41 unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); 42 void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); 43 void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); 44 #endif /* __ASSEMBLY__ */ 45 46 #endif /* __CORTEX_A75_H__ */ 47