1d40ab484SDavid Wang /* 2*7f152ea6SSona Mathew * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3d40ab484SDavid Wang * 4d40ab484SDavid Wang * SPDX-License-Identifier: BSD-3-Clause 5d40ab484SDavid Wang */ 6d40ab484SDavid Wang 743534997SAntonio Nino Diaz #ifndef CORTEX_A75_H 843534997SAntonio Nino Diaz #define CORTEX_A75_H 943534997SAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 11d40ab484SDavid Wang 12d40ab484SDavid Wang /* Cortex-A75 MIDR */ 1343534997SAntonio Nino Diaz #define CORTEX_A75_MIDR U(0x410fd0a0) 14d40ab484SDavid Wang 15d40ab484SDavid Wang /******************************************************************************* 16d40ab484SDavid Wang * CPU Extended Control register specific definitions. 17d40ab484SDavid Wang ******************************************************************************/ 18d40ab484SDavid Wang #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19d40ab484SDavid Wang #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 20d40ab484SDavid Wang 21b8a25bbbSDimitris Papastamos /******************************************************************************* 22b8a25bbbSDimitris Papastamos * CPU Auxiliary Control register specific definitions. 23b8a25bbbSDimitris Papastamos ******************************************************************************/ 24b8a25bbbSDimitris Papastamos #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 25b8a25bbbSDimitris Papastamos 26a69817edSAntonio Nino Diaz #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) 27b8a25bbbSDimitris Papastamos 28d40ab484SDavid Wang /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ 2943534997SAntonio Nino Diaz #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) 30d40ab484SDavid Wang 311a74e4a8SAntonio Nino Diaz #define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) 320319a977SDimitris Papastamos 330319a977SDimitris Papastamos /* 340319a977SDimitris Papastamos * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are 350319a977SDimitris Papastamos * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are 360319a977SDimitris Papastamos * programmable by programming the appropriate Event count bits in 370319a977SDimitris Papastamos * CPUAMEVTYPER<n> register and are disabled by default. Platforms may 380319a977SDimitris Papastamos * enable this with suitable programming. 390319a977SDimitris Papastamos */ 40714b21ffSDimitris Papastamos #define CORTEX_A75_AMU_NR_COUNTERS U(5) 41714b21ffSDimitris Papastamos #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) 42714b21ffSDimitris Papastamos #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) 430319a977SDimitris Papastamos 44d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 4553bfb94eSDimitris Papastamos #include <stdint.h> 4653bfb94eSDimitris Papastamos 4753bfb94eSDimitris Papastamos uint64_t cortex_a75_amu_cnt_read(int idx); 4853bfb94eSDimitris Papastamos void cortex_a75_amu_cnt_write(int idx, uint64_t val); 4953bfb94eSDimitris Papastamos unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); 5053bfb94eSDimitris Papastamos unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); 5153bfb94eSDimitris Papastamos void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); 5253bfb94eSDimitris Papastamos void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); 53*7f152ea6SSona Mathew 54*7f152ea6SSona Mathew #if ERRATA_A75_764081 55*7f152ea6SSona Mathew long check_erratum_cortex_a75_764081(long cpu_rev); 56*7f152ea6SSona Mathew #endif /* ERRATA_A75_764081 */ 57*7f152ea6SSona Mathew 58d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 5953bfb94eSDimitris Papastamos 6043534997SAntonio Nino Diaz #endif /* CORTEX_A75_H */ 61