1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A73_H 8 #define CORTEX_A73_H 9 10 /* Cortex-A73 midr for revision 0 */ 11 #define CORTEX_A73_MIDR 0x410FD090 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ 17 18 #define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) 19 20 /******************************************************************************* 21 * L2 Memory Error Syndrome register specific definitions. 22 ******************************************************************************/ 23 #define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ 24 25 /******************************************************************************* 26 * CPU implementation defined register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 29 30 #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (1 << 3) 31 32 #endif /* CORTEX_A73_H */ 33