12460ac18SYatharth Kochar /* 2*4c700c15SGovindraj Raja * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. 32460ac18SYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 52460ac18SYatharth Kochar */ 62460ac18SYatharth Kochar 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A73_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A73_H 92460ac18SYatharth Kochar 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 122460ac18SYatharth Kochar /* Cortex-A73 midr for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A73_MIDR U(0x410FD090) 142460ac18SYatharth Kochar 152460ac18SYatharth Kochar /******************************************************************************* 162460ac18SYatharth Kochar * CPU Extended Control register specific definitions. 172460ac18SYatharth Kochar ******************************************************************************/ 182460ac18SYatharth Kochar #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ 192460ac18SYatharth Kochar 201a74e4a8SAntonio Nino Diaz #define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6) 212460ac18SYatharth Kochar 2284629f2fSNaga Sureshkumar Relli /******************************************************************************* 2384629f2fSNaga Sureshkumar Relli * L2 Memory Error Syndrome register specific definitions. 2484629f2fSNaga Sureshkumar Relli ******************************************************************************/ 2584629f2fSNaga Sureshkumar Relli #define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ 2684629f2fSNaga Sureshkumar Relli 27b8a25bbbSDimitris Papastamos /******************************************************************************* 28b8a25bbbSDimitris Papastamos * CPU implementation defined register specific definitions. 29b8a25bbbSDimitris Papastamos ******************************************************************************/ 30b8a25bbbSDimitris Papastamos #define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 31b8a25bbbSDimitris Papastamos 321a74e4a8SAntonio Nino Diaz #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) 33b8a25bbbSDimitris Papastamos 3425278eabSLouis Mayencourt #define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1 3525278eabSLouis Mayencourt 36e6cab15dSLouis Mayencourt #define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 37e6cab15dSLouis Mayencourt 387352f329Skenny liang /******************************************************************************* 397352f329Skenny liang * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs 407352f329Skenny liang ******************************************************************************/ 4189632e6aSBalint Dobszay #ifndef __ASSEMBLER__ 427352f329Skenny liang DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) 4389632e6aSBalint Dobszay #endif /* __ASSEMBLER__ */ 447352f329Skenny liang 45c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A73_H */ 46